Abstract: A circuit system includes a platform baseboard, an integrated circuit coupled to the platform baseboard, and an auxiliary control board mounted on the platform baseboard. The auxiliary control board includes an interface device that is in communication with the integrated circuit through the platform baseboard. The auxiliary control board can perform power sequencing functions for the circuit system. The auxiliary control board can also perform telemetry gathering, hardware security functions, and configuration of the integrated circuit.

Abstract: A circuit system includes a platform baseboard, an integrated circuit coupled to the platform baseboard, and an auxiliary control board mounted on the platform baseboard. The auxiliary control board includes an interface device that is in communication with the integrated circuit through the platform baseboard. The auxiliary control board can perform power sequencing functions for the circuit system. The auxiliary control board can also perform telemetry gathering, hardware security functions, and configuration of the integrated circuit.

Abstract: A computer-implemented method, system, and computer program product for cross-domain mapping between a business process modeler domain and an implementation domain are provided. The method includes accessing a business concept registry on a data storage device including business concepts with mapping for the business process modeler domain and the implementation domain. The method also includes creating a model with one or more of the business concepts interconnected to represent a business process in the business process modeler domain, and exporting the model from the business process modeler domain to the implementation domain according to the business concept mapping of the business concept registry.

Abstract: Described herein is the fusion of two families of unique carbon-containing molecules that readily disregard the tendency of carbon to form four chemical bonds, namely N-heterocyclic carbenes (NHCs) and carborane anions. Deprotonation of an anionic imidazolium salt with lithium diisopropylamide at room temperature leads to a mixture of lithium complexes of C-2 and C-5 dianionic NHC constitutional isomers as well as a trianionic (C-2, C-5) adduct. Judicious choice of the base and reaction conditions allows for the selective formation of all three stable polyanionic carbenes. In solution, the so-called abnormal C-5 NHC lithium complex slowly isomerizes to the normal C-2 NHC, and the process can be proton catalyzed by the addition of the anionic imidazolium salt. These results indicate that the combination of two unusual forms of carbon atoms can lead to unexpected chemical behavior, and that this strategy paves the way for the development of a broad new generation of NHC ligands for catalysis.

Abstract: Described herein is the fusion of two families of unique carbon-containing molecules that readily disregard the tendency of carbon to form four chemical bonds, namely N-heterocyclic carbenes (NHCs) and carborane anions. Deprotonation of an anionic imidazolium salt with lithium diisopropylamide at room temperature leads to a mixture of lithium complexes of C-2 and C-5 dianionic NHC constitutional isomers as well as a trianionic (C-2, C-5) adduct. Judicious choice of the base and reaction conditions allows for the selective formation of all three stable polyanionic carbenes. In solution, the so-called abnormal C-5 NHC lithium complex slowly isomerizes to the normal C-2 NHC, and the process can be proton catalyzed by the addition of the anionic imidazolium salt. These results indicate that the combination of two unusual forms of carbon atoms can lead to unexpected chemical behavior, and that this strategy paves the way for the development of a broad new generation of NHC ligands for catalysis.

Abstract: A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit.

Abstract: An embodiment of the present invention implements a linear feedback shift register (LFSR) as a counting device for an integrator of a DFE circuit. In embodiments of the present invention, the particular count sequence need not be known, instead only boundary values need be known. For example, for a LFSR having a predetermined count sequence, a digital integrator controller need not know every value of the count sequence. Instead, the digital integrator controller detects predetermined boundary values such as a minimum or maximum count.

Abstract: An integrated circuit is presented. The integrated circuit includes a selection circuit that selects a reference voltage and an output voltage associated with a number of adjustable voltage regulators connected to the selection circuit. The integrated circuit also has an analog to digital converter, which converts the selected output voltage and the reference voltage to a digital representation. An analog state machine of the integrated circuit receives the digital representation from the analog to digital converter and compares the selected output voltage with the reference voltage.

Abstract: Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

Abstract: One embodiment relates an equalizer which includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to apply a first gain at a characteristic frequency while attenuating frequencies in a low frequency range. The second amplifier stage is configured to apply a second gain at the frequencies in the low frequency range. The first amplifier stage may be configured before the second amplifier stage, or vice versa. Another embodiment relates to a method of linear equalization. Another embodiment relates to an amplifier which may be used for linear equalization. Other embodiments, aspects, and features are also disclosed.

Abstract: The ability of clock and data recovery (“CDR”) circuitry on an integrated circuit (“IC”) to handle jitter in a serial data input signal can be tested by using transmitter circuitry on the IC to produce a serial data output signal whose time base has been subjected to modulation. Loop-back circuitry on the IC may be used to apply the serial data output signal to the CDR circuitry as the serial data input signal of the CDR circuitry. Modulation circuitry on the IC may be used to cause the above modulation of the time base of the serial data output signal.

Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Abstract: Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.

Abstract: Integrated circuits with communications circuitry are provided. The communications circuitry may include at least first and second flip-flops connected in a chain along a data path. The first flip-flop may be controlled by a clock signal. The clock signal may be fed to a delay matching circuit. The delay matching circuit may provide a delayed version of the clock signal that controls the second flip-flop. The delay provided by the delay matching circuit may be equal to a clock-to-output delay of the first flip-flop. The delay matching circuit may have the same physical arrangement as the first flip-flop. The first and second flip-flops and the delay matching circuit may include dynamic sense amplifier flip-flops. The delay matching circuit may have an input that receives a high signal, a control input that receives the clock signal, and an output over which the delayed clock signal is provided.

Abstract: One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer.

Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Abstract: One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

Abstract: Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.