Patents by Inventor Allen Chu

Allen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190248700
    Abstract: A low-emissivity (low-E) coating on a substrate (e.g., glass substrate) includes at least first and second infrared (IR) reflecting layers (e.g., silver based layers) that are spaced apart by contact layers (e.g., NiCr based layers), a layer comprising silicon nitride, and an absorber layer of or including a material such as niobium zirconium which may be oxided and/or nitrided. The absorber layer is designed to allow the coated article to realize glass side reflective (equivalent to exterior reflective in an IG window unit when the coating is on surface #2 of the IG unit) grey color. In certain example embodiments, the coated article (monolithic form and/or in IG window unit form) has a low visible transmission (e.g., from 20-45%, more preferably from 22-39%, and most preferably from 25-37%). In certain example embodiments, the coated article may be heat treated (e.g., thermally tempered and/or heat bent).
    Type: Application
    Filed: October 18, 2016
    Publication date: August 15, 2019
    Applicants: GUARDIAN GLASS, LLC, GUARDIAN GLASS HOLDING S.P.C.
    Inventors: ARITRA BISWAS, BRENT BOYCE, ALLEN CHU, PHILIP J. LINGLE, KENNETH LORD, MUNISWAMI NAIDU, KRISHNA SWAMYNAIDU
  • Publication number: 20180127307
    Abstract: In certain example embodiments, a coated article includes a carbon-doped zirconium based layer before heat treatment (HT). The coated article is heat treated sufficiently to cause the carbon-doped zirconium oxide and/or nitride based layer to result in a carbon-doped zirconium oxide based layer that is scratch resistant and/or chemically durable. The doping of the layer with carbon (C) has been found to improve wear resistance.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 10, 2018
    Inventors: Jens-Peter MULLER, Jean VIEIRA, Bernd DISTELDORF, Allen CHU, Jijun LAO, Yiwei LU, Vijayen S. VEERASAMY
  • Patent number: 9317389
    Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 19, 2016
    Assignee: INTEL CORPORATION
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen Chu
  • Publication number: 20150006971
    Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen Chu
  • Patent number: 8540594
    Abstract: The illuminated nock assembly of the present invention attaches to the shaft of an arrow to assist in tracking the trajectory of the arrow in flight and in locating the arrow after flight. The illuminated nock assembly includes a housing having two separate parts, lighting components and a power source. The lighting components are illuminated when arrow shaft is placed on the housing.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: September 24, 2013
    Assignee: The Allen Company, Inc.
    Inventor: Allen Chu
  • Publication number: 20110312453
    Abstract: The illuminated nock assembly of the present invention attaches to the shaft of an arrow to assist in tracking the trajectory of the arrow in flight and in locating the arrow after flight. The illuminated nock assembly includes a housing having two separate parts, lighting components and a power source. The lighting components are illuminated when arrow shaft is placed on the housing.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 22, 2011
    Inventor: Allen Chu
  • Patent number: 6813342
    Abstract: A system, method and computer program product are provided for determining an area code during voice activated dialing. Initially, utterances are received from the user during a session via a speech recognition portal. Such utterances are indicative of a third party. A speech recognition process is then performed on the utterances to interpret the utterances. A phone number is then identified based on the utterances. It is then determined whether the phone number includes an area code. If it is determined that the phone number does not include an area code, the area code is inferred. The inferred area code may then be outputted to the user. The user is then prompted to confirm the inferred area code. The phone number is then dialed with the inferred area code upon the receipt of confirmation from the user.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: November 2, 2004
    Assignee: BeVocal, Inc.
    Inventors: Wesley Allen Chu, Susan Yeh Yung, Ryan J. Bush
  • Patent number: 6803301
    Abstract: A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: October 12, 2004
    Assignee: Infineon Technologies Richmond, LP
    Inventors: Ulrich Zimmerman, Allen Chu, Robert Trahan
  • Publication number: 20030234435
    Abstract: A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.
    Type: Application
    Filed: June 19, 2002
    Publication date: December 25, 2003
    Applicant: Infineon Technologies Richmond, LP
    Inventors: Ulrich Zimmerman, Allen Chu, Robert Trahan