Abstract: The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect over each cell, wherein the first metal layer comprises local core cell nodes and the second metal layer comprises power/ground. The RAM is also fabricated with metal junction points on the first metal layer in at least a portion of the intersections. Thereafter, the RAM is reconfigured to a ROM by forming vias between the intersections of the first and second metal layers over the junction points to connect the first metal layer to the second metal layer.

Abstract: The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect over each cell, wherein the first metal layer comprises local core cell nodes and the second metal layer comprises power/ground. The RAM is also fabricated with metal junction points on the first metal layer in at least a portion of the intersections. Thereafter, the RAM is reconfigured to a ROM by forming vias between the intersections of the first and second metal layers over the junction points to connect the first metal layer to the second metal layer.

Abstract: A circuit for matching sense amplifier trigger signal timing to data bit line separation timing in a self-timed memory array includes: a source of a self-timed word line signal for a self-timed memory array; a transmission gate coupled to the source of the self-timed word line signal for propagating a timing delay and a ramp rate of the self-timed word line signal in response to a corresponding self-timed word line enable signal; and a selectable number of one or more self-timed pull-down core cells for summing a self-timed bit line drive current of each of the selectable number of one or more self-timed pull-down core cells to generate a sense amplifier trigger signal.