Abstract: A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.

Abstract: A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.

Abstract: A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.

Abstract: A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.

Abstract: In a method, various operations are performed based on a voltage line coupled with a plurality of memory cells. Storage nodes of the plurality of memory cells are caused to change to a first logical value. Another first logical value is applied to a plurality of data lines. Each data line of the plurality of data lines carries data for each memory cell of the plurality of memory cells. A control line of the plurality of memory cells is activated. A first voltage value is applied to the voltage line. The first voltage value causes the another first logical value on the plurality of data lines to be transferred to the storage nodes of the plurality of memory cells.