Patents by Inventor Allen Hairston

Allen Hairston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060125940
    Abstract: An imaging system configured with readout circuit redundancy is disclosed. Pixel data from a particular column can be steered around a defective readout circuit to an operational readout circuit. Thus, larger imaging arrays which are generally more prone to common column circuitry defects are enabled. In addition, imaging systems configured with significant on-chip signal processing, which are also more prone to common column circuitry defects, are enabled. The occurrence of lost pixel data from an entire column is eliminated or otherwise reduced, thereby increasing overall operability and yield of the imaging system. The system can be implemented on a single chip or a chip set.
    Type: Application
    Filed: December 14, 2004
    Publication date: June 15, 2006
    Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
    Inventors: Rosanne Tinkler, Allen Hairston
  • Publication number: 20060044071
    Abstract: Described techniques extend (e.g., by a factor of 2) the dynamic range of voltage swing for amplifiers and other integrated circuits (e.g., buffers) that are fabricated using lower voltage rated semiconductor processes. Such processes include, for instance, thin gate oxide MOS, and other semiconductor processes that provide desirable features that are typically not associated with high voltage processes, such as increased radiation hardness, higher speed logic, and compactness. Thus, relatively large dynamic range is enabled for integrated circuits fabricated using feature-rich lower voltage rated semiconductor processes.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 2, 2006
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.
    Inventor: Allen Hairston
  • Publication number: 20050275446
    Abstract: Techniques for precise removal of offset charge associated with the reset switch of an integration circuit are disclosed. Offset cancellation circuitry includes a single reset offset subtraction circuit and a replica integrator, which is configured identically to the integrators to be offset cancelled. An offset charge is generated by the circuitry and capacitively coupled to the target integrators. This generated offset charge causes voltage at the input node of each target integrator to substantially match the desired starting voltage level of the targeted integration process. Minimal additional space and circuitry is needed. All of the undesired offset charge is cancelled, without canceling any of the desired input current.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.
    Inventor: Allen Hairston