Abstract: Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

Abstract: Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

Abstract: Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Abstract: An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word is associated with at least one transaction performed on a unit. A controller controls iterating the generation of the data syndrome.

Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules.

Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules.

Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself.

Abstract: An improved method for cleaning heat exchangers, wherein a first cleaning liquid is used to remove a majority of the accumulated sludge and deposits from the surfaces of the heat exchanger, and a second cleaning liquid is used to remove deposits from the crevice regions of the heat exchanger. Boiling may be induced in the crevices between the tubes and the tube support plates by venting of the secondary side while heating through the primary side of the heat exchanger. Repeated venting as the water level is lowered results in crevice boiling at each tube support plate. Mechanical cleaning techniques such as pressure pulse cleaning may be utilized with either or both of the cleaning liquids. Additional liquids may be introduced into the heat exchanger to provide further cleaning action or to facilitate flushing of the previous cleaning liquids.

Abstract: An improved method for cleaning heat exchangers, wherein a first liquid containing a cleaning agent is used to remove substantially all of the accumulated sludge and deposits from the surfaces of the heat exchanger, and a second liquid containing a cleaning agent is used to remove deposits from the crevice regions of the heat exchanger. The concentration of cleaning agent in the second liquid and/or the duration of exposure for the second liquid are preferably greater than those of the first liquid, because the risk of corrosion is reduced as a result of a lower concentration of ferric ions in the second liquid. Furthermore, improved crevice region cleaning is obtained with the second liquid because the available cleaning agent is not depleted by the large volume of sludge and deposits removed by the first liquid. Mechanical cleaning techniques such as pressure pulse cleaning may be utilized with either or both of the cleaning liquids.

Abstract: A device for creating a corrosive condition and monitoring that condition, adapted for use in active fluid heat exchangers, has a sealed tube having corrosion sites spaced apart on its exterior. Structure positioned on the outside of the tube at the corrosion sites provide crevices for retaining corrosive sludges in contact with the corrosion sites. The interior of the tube is pressurized with a gas to stress the tube thereby accelerating corrosion of the surface. Heat is provided to the corrosion sites from within the tube when placed within a fluid reservoir, such as the secondary side of a fluid heat exchanger. The heat concentrates corrosive chemicals at the corrosion sites, also accelerating corrosion. Electronic probes can be mounted in proximity to the corrosion sites for real time monitoring of the progress of corrosion.

Abstract: A method and apparatus for instruction prefixing selectively reconfigures certain of the instructions in the microprocessor's instruction set so as to alter the nature of the operation performed by the instruction and/or the designation of operand or result locations accessed by the operation. A prefix instruction is inserted ahead of a "using" instruction and an operational parameter of the using instruction is modified in accordance with the contents of the prefix instruction. In one application, the prefix instruction may be used to specify a register location for storage of a result of the using instruction's operation or retrieval of an operand. In other applications, the prefix instruction may be used to modify other aspects of instruction execution.

Abstract: A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is computed based, in part, on the state of the processor available flag. If the processor is available, indicating that it is not currently working on a task, there is no need to preserve the processor state information, and the state-saving portions of the interrupt processing routines are bypassed. On the other hand, if the processor is not available, indicating that the it is engaged in a task, the state information must be preserved so that the processor can return to the task after the interrupt is processed. In this case, the state-saving portions of the interrupt processing routines are not bypassed.

Abstract: An improved method for removing sludge and corrosion products from the interior of a heat exchanger vessel, such as a nuclear steam generator, which comprises the steps of generating a series of pressure pulses within a liquid chelate-containing chemical cleaning agent after the agent has been introduced into the interior of the vessel to create shock waves in the liquid for dislodging, dissolving and fluidizing sludge and corrosion products. The liquid chemical cleaning agent is removed from the vessel after only about 10 to 70 percent of what would have been its normal residence time without the pressure pulses.

Abstract: A method for reducing interrupt processing overhead is applied in situations when it is not necessary to preserve processor state information. A flag is provided to indicate whether or not the processor is available. Upon recognition of an interrupt, an interrupt vector address is computed based, in part, on the state of the processor available flag. If the processor is available, indicating that it is not currently working on a task, there is no need to preserve the processor state information, and the state-saving portions of the interrupt processing routines are bypassed. On the other hand, if the processor is not available, indicating that it is engaged in a task, the state information must be preserved so that the processor can return to the task after the interrupt is processed. In this case, the state-saving portions of the interrupt processing routines are not bypassed.

Abstract: In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is fetched, the operation specified by the first instruction is performed and the results of the operation are stored, including the state of the nullification field. The second instruction is fetched and the operation specified by the second operation is performed. However, conditional upon the state of the nullification field of the first instruction, results, errors, traps and interrupts of the second instruction are not stored in the computer system.

Abstract: Methods and apparatus are provided for performing multi-gauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel processing of individual bytes or half words of data words without requiring that the processor's mode be separately controlled. A byte/half word mode flag is provided to control the "width" of narrow gauge operation. Add partial, substract partial and compare partial instructions operate on corresponding bytes or half words of two operands and return independent byte or half word results. Multiply partial instructions multiply byte or half word multiplicands by a common multiplier and return independent byte or half word products. The multi-gauge arithmetic operations of the present invention have particular application to graphics processing where repetitive operations are performed on large arrays of pixel data.

Abstract: In a computer device in accordance with the preferred embodiment of the invention, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing conditional results. Additionally, it also is capable of implementing slightly more general operations than simply storing a zero or one value of a comparison. Basically, the instruction set in accordance with the invention compares two operands and unconditionally stores a zero, which represents a Boolean "false", into a selected destination. The instruction set then conditionally nullifies the instruction following it, thus effecting a highly efficient execution of a sequence of instructions compared to the prior art.

Abstract: A method and apparatus for efficient branching within a central processing unit with overlapped fetch and execute cycles which optimizes the efficient fetching of instructions.