Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Abstract: An apparatus includes a control module and an activity module. The control module provides error control information based on a target number of bits and an actual number of bits required to pack at least one compressed block of image information. The activity module provides a quantization factor based on the error control information and a complexity value of the at least one compressed block of image information. The quantization factor is used to pack the at least one compressed block of image information into a bitstream comprising the target number of bits.

Abstract: An apparatus for response time compensation includes a compression module, a decompression module, a display element response time compensation module, and a bypass control module. The compression module compresses a current frame to produce a compressed previous frame of image information. The decompression module decompresses the compressed previous frame of image information to produce a decompressed previous frame of image information. The display element response time compensation module provides display compensation information for a display based on the current frame and the decompressed previous frame. The bypass control module causes the current frame information to selectively bypass the compression module, the decompression module, and/or the display element response time compensation module based on display mode information.

Abstract: An apparatus for a response time compensation system includes a plurality of complexity modules and a motion vector module. The complexity modules determine a plurality of complexity values based on current image information and prior image information. The motion vector module determines a desired complexity value based on a lowest of complexity values. The motion vector determines a desired motion vector based on the lowest of the plurality of complexity values. The desired complexity value and the desired motion vector are used to compress the current image information into a compressed bitstream. The compressed bitstream is used by the response time compensation system to provide display element response time compensation information for a display.

Abstract: A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graphics data stream includes graphics data in a second format. The video data of the video data stream is scaled based on a ratio between the first format and a selected video format to produce a scaled video stream. Similarly, the graphics data of the graphics data stream is scaled based on a ratio between the second format and a selected graphics format in order to produce a scaled graphics stream. The scaled video stream and the scaled graphics stream are then merged to produce a video graphics output stream.

Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Abstract: A system and methods are shown for protecting registers among data processors. Sets of protected registers on data processors are used for enabling security features related to the protection of multimedia content. The security features relate to techniques used to prevent the multimedia content from being successfully copied. The data processors also include general registers used for general processor features and settings. Commands to control the general and security features are placed on a non-secure data bus. The commands related to the general settings are passed directly to the data processors' registers, allowing direct access and control. The commands related to the security settings are addressed to a secure processor. The secure processor processes the commands to determine whether the source application that generated the commands is authorized to make such changes.

Abstract: A system and methods are provided for maintaining a timing relationship among data packets associated with a single program of a multiple program transport stream. Select data relating to a single multimedia program is selected from the multiple program transport stream. Timestamps, used to represent the time on a system time clock when particular packets are received, are attached to data packets from the single program. The time-stamped packets are stored in memory. When accessed back from memory, the timestamps are used to determine when to present the data of the packets. The data can then be used to construct a transport stream made up of only the data related to the selected single program.

Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Abstract: A method and apparatus for storing and displaying video image data in a video graphics system is accomplished by receiving a video data stream, where the video data stream includes compressed video image data. The video image stream is parsed to separate the compressed video image data from other data within the data stream. The compressed video image data is decompressed to produce video image data that includes a luminosity plane, a first color plane, and a second color plane. Members of the first and second color planes are compacted together to form color pairs where a plurality of the color pairs form a color line. Each of the color lines is interleaved with at least one luminosity line to produce an interleaved plane. The interleaved plane is stored in memory. Portions of the interleaved video image data are retrieved from the interleaved plane. The portions are structured such that video image data that are located near each other within the memory are fetched together.

Abstract: A method and apparatus for storing and displaying multiple graphical images in a mixed video and graphics display is accomplished by determining an amount of memory sufficient to display a single graphics image in a subset of the display. Once the amount of memory required for a single image is determined, the pre-allocated portion of memory for graphics images is divided into an array. Graphics images are then rendered and stored within this array. One of the pre-rendered images is selected by a control block, wherein the selection is based on registers or parameters referenced by the control block. A display output engine fetches the selected one of the plurality of pre-rendered graphics images that is stored within the array and combines the selected graphics image with the video data stream to produce a display output stream. The display output stream is then fed to a display device that displays the graphics image.