Abstract: An ISDN interface is provided on a card, which is adapted for mounting in a terminal computer and which is operable to exchange data with a terminal computer and an ISDN. The ISDN interface card includes a protocol processor that is programmable to process data encoded in accordance with a number of different protocols and a digital signal processor that is programmable for data compression, encryption and facsimile applications, and u-law and a-law conversion, among other applications. The ISDN card dynamically allocates data calls between one or two B-channels to achieve a data transmission rate of 128 kbps. A power supply with a ring generator is provided to allow for the use of an analog telephone with the ISDN card. The ISDN card is programmable to allow users to create customized screens for various call processes, and to allow for the updating of a flash ROM coupled to the protocol processor through the terminal computer and the ISDN.

Abstract: A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA addresses which may match the 16 K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

Abstract: A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 1 megabyte address space to be selectively mapped to a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

Abstract: A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses in 16K blocks which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.