Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Abstract: A means and method for forming a single tub transistor, such as for example a vertical NPN bipolar transistor surrounded by an isolation wall, is described. Multiple polysilicon and dielectric layers are employed in conjunction with a master mask and with isotropic and anisotropic etching procedures to define the contacts and active regions of the device without resorting to precision alignments. Sub-micron lateral device contacts are easily achieved even with comparatively coarse lithographic methods through use of sidewall spacers for controlled narrowing of critical device openings. The finished device is especially compact, has low resistance contacts for its size, and provides very high speed operation.