Patents by Inventor Allen KE

Allen KE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Etch profile control of interconnect structures
    Patent number: 11569125
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Etch Profile Control of Interconnect Structures
    Publication number: 20220093457
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Etch profile control of interconnect structures
    Patent number: 11195750
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Tawiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
    Publication number: 20200328113
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
  • Etch profile control of interconnect structures
    Patent number: 10707123
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
    Publication number: 20190096754
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen KE, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
  • ETCH PROFILE CONTROL OF INTERCONNECT STRUCTURES
    Publication number: 20180315648
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen KE, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo