Abstract: A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

Abstract: A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

Abstract: A computer system having a plurality of processors where each of the processors is dynamically assigned for execution of tasks based upon either performance or reliability.

Abstract: A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.

Abstract: A data driven clock recovery system comprising a viterbi detector for detecting data and tentatively deciding the closest approximation, and a circuit for retrieving the tentative decision in stages. Preferably, the clock recovery system further comprises a combination series-parallel comparison circuit for selecting one value of a set of values for input to the viterbi and for applying said one value to the viterbi.

Abstract: A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

Abstract: A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.

Abstract: A method and structure for a system for decoding a parity encoded data signal. A multiplexor has a first input adapted to receive said data signal. A plurality of decoders are connected to the multiplexor. The multiplexor uses the decoders in a decoding process to decode the data signal into a corrected data signal and to repeat the decoding process on the corrected data signal. The multiplexor can include a second input that receives the corrected data signal output by the decoders.

Abstract: A computer system having a plurality of processors where each of the processors is dynamically assigned for execution of tasks based upon either performance or reliability.

Abstract: A data driven clock recovery system comprising a viterbi for detecting data and tentatively deciding the closest approximation, and a circuit for retrieving the tentative decision in stages. Preferably, the clock recovery system further comprises a combination series-parallel comparison circuit for selecting one value of a set of values for input to the viterbi and for applying said one value to the viterbi.

Abstract: A computer system having a plurality of processors where each of the processors is dynamically assigned for execution of tasks based upon either performance or reliability.

Abstract: A method and apparatus for maximum likelihood detection of a sequential stream of binary bits. 2N binary states (N≧2) are projected onto a trellis at a sequence of times. Two branches to each binary state at time Ti+1 from a closest previous time Ti are identified (i≧N). There are 2N+1 such branches between Ti and Ti+1. A state metric for each of the 2N binary states at Ti and a branch metric for each of the 2N+1 branches between Ti and Ti+1 are provided. An illegal branch and a legal branch to a state S1 at time Ti+1 are so designated. A state metric is computed at each of the 2N binary states at time Ti+1 as a function of: the state metrics at Ti, the branch metrics between Ti and Ti+1, and the 2 branches to state S1.