Patents by Inventor Allen Russell Andrews
Allen Russell Andrews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359377Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
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Patent number: 11740815Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.Type: GrantFiled: August 30, 2021Date of Patent: August 29, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
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Patent number: 11216190Abstract: A system and method for managing input output queue pairs. In some embodiments, the method includes calculating a system utilization ratio, the system utilization ratio being a ratio of: an arrival rate of input output requests, to a service rate; determining whether: the system utilization ratio has exceeded a first threshold utilization during a time period exceeding a first threshold length, and adding a new queue pair is expected to improve system performance; and in response to determining: that the system utilization ratio has exceeded the first threshold utilization during a time period exceeding the first threshold length, and that adding a new queue pair is expected to improve system performance: adding a new queue pair.Type: GrantFiled: August 9, 2019Date of Patent: January 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra G. Sampath, T. David Evans, Clay Mayers
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Publication number: 20210389891Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
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Patent number: 11144226Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.Type: GrantFiled: July 1, 2019Date of Patent: October 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
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Publication number: 20200387312Abstract: A system and method for managing input output queue pairs. In some embodiments, the method includes calculating a system utilization ratio, the system utilization ratio being a ratio of: an arrival rate of input output requests, to a service rate; determining whether: the system utilization ratio has exceeded a first threshold utilization during a time period exceeding a first threshold length, and adding a new queue pair is expected to improve system performance; and in response to determining: that the system utilization ratio has exceeded the first threshold utilization during a time period exceeding the first threshold length, and that adding a new queue pair is expected to improve system performance: adding a new queue pair.Type: ApplicationFiled: August 9, 2019Publication date: December 10, 2020Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra G. Sampath, T. David Evans, Clay Mayers
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Publication number: 20200326868Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.Type: ApplicationFiled: July 1, 2019Publication date: October 15, 2020Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
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Patent number: 9336168Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.Type: GrantFiled: September 25, 2015Date of Patent: May 10, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
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Publication number: 20160011997Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.Type: ApplicationFiled: September 25, 2015Publication date: January 14, 2016Inventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
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Patent number: 9183167Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.Type: GrantFiled: November 22, 2013Date of Patent: November 10, 2015Assignee: EMULEX CORPORATIONInventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
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Publication number: 20140082244Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.Type: ApplicationFiled: November 22, 2013Publication date: March 20, 2014Applicant: Emulex Design & Manufacturing CorporationInventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
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Patent number: 8635387Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.Type: GrantFiled: October 9, 2009Date of Patent: January 21, 2014Assignee: Emulex Design & Manufacturing CorporationInventors: Qiang Liu, Allen Russell Andrews, David Bradley Baldwin
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Publication number: 20110087814Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: Emulex Design & Manufacturing CorporationInventors: Qiang LIU, Allen Russell Andrews, David Bradley Baldwin