Abstract: A DC-DC converter includes a substrate having opposing first and second sides, a power stage attached to the first side of the substrate and having active semiconductor components operable to provide an output phase of the DC-DC converter, an inductor attached to the first side of the substrate and electrically connected to the power stage through a first metal trace at the first side of the substrate, and a plurality of electrically conductive vias extending through the substrate from the first side to the second side. The vias are electrically connected to the first metal trace. At least some of the vias are disposed at least partly under the power stage. A corresponding method of assembling such a DC-DC converter also is disclosed.

Abstract: A DC-DC converter includes a substrate having opposing first and second sides, a power stage attached to the first side of the substrate and having active semiconductor components operable to provide an output phase of the DC-DC converter, an inductor attached to the first side of the substrate and electrically connected to the power stage through a first metal trace at the first side of the substrate, and a plurality of electrically conductive vias extending through the substrate from the first side to the second side. The vias are electrically connected to the first metal trace. At least some of the vias are disposed at least partly under the power stage. A corresponding method of assembling such a DC-DC converter also is disclosed.

Abstract: A method of rule-based register checking for a digital voltage regulator controller includes: defining register settings for the digital voltage regulator via a GUI (graphical user interface) based controller parameter configuration system; accessing a rule-based checker by the GUI based configuration system to check for rule violations in the register settings; and uploading the register settings from the GUI based configuration system to the digital voltage regulator controller after checking the register settings for rule violations. A non-transitory computer readable medium storing a computer program operable to implement the rule-based register checking is also provided.

Abstract: A DC-DC converter includes a substrate having opposing first and second sides, a power stage attached to the first side of the substrate and having active semiconductor components operable to provide an output phase of the DC-DC converter, an inductor attached to the first side of the substrate and electrically connected to the power stage through a first metal trace at the first side of the substrate, and a plurality of electrically conductive vias extending through the substrate from the first side to the second side. The vias are electrically connected to the first metal trace. At least some of the vias are disposed at least partly under the power stage. A corresponding method of assembling such a DC-DC converter also is disclosed.

Abstract: A method of rule-based register checking for a digital voltage regulator controller includes: defining register settings for the digital voltage regulator via a GUI (graphical user interface) based controller parameter configuration system; accessing a rule-based checker by the GUI based configuration system to check for rule violations in the register settings; and uploading the register settings from the GUI based configuration system to the digital voltage regulator controller after checking the register settings for rule violations. A non-transitory computer readable medium storing a computer program operable to implement the rule-based register checking is also provided.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.