Abstract: One or more flow control modules, implemented on various types of network topologies, provide a number of functionalities for controlling the flow of IP packets (such as TCP/IP packets) over a network connection. The flow control modules may be implemented within a sender and/or receiver or may be deployed into a network as a separate device without requiring significant additional resources.

Abstract: One or more flow control modules, implemented on various types of network topologies, provide a number of functionalities for controlling the flow of IP packets (such as TCP/IP packets) over a network connection. The flow control modules may be implemented within a sender and/or receiver or may be deployed into a network as a separate device without requiring significant additional resources.

Abstract: One or more flow control modules, implemented on various types of network topologies, provide a number of functionalities for controlling the flow of IP packets (such as TCP/IP packets) over a network connection. The flow control modules may be implemented within a sender and/or receiver or may be deployed into a network as a separate device without requiring significant additional resources.

Abstract: Network endpoints using TCP/IP operate to determine the maximum transmission unit (MTU) of the path between them. This determination is done so as to avoid the expensive IP fragmentation that will occur when transitting links with a smaller MTU size. The standard method of determining the path MTU (PMTU) has several known deficiencies, including: inefficient use of bandwidth as proper operation will likely result in the loss of one or more packets and difficulty of implementation as the reverse channel communication mechanism, reception of ICMP messages indicating the discarding of unfragmentable packets, is frequently blocked by firewalls and other security apparatus. A method of determining the PMTU between intermediate proxies is disclosed that does not require reception of ICMP messages or the inefficient use of bandwidth due to the presumed dropping of packets with valid data.

Abstract: The present invention comprises a disposable hygiene device with a toilet seat with a top and bottom surfaces, where the toilet seat folds for storage before or after use. A receptacle is attached to the bottom surface of the toilet seat. After use, an adhesive on the top surface of the toilet seat is exposed by the removal of a protective layer. The toilet seat may then be folded onto itself to seal the hygiene device for easy disposal. The toilet seat may also include handles or an extension to ease proper orientation and use of the disposable hygiene device. The present invention also includes hygiene stations, preferably portable, that may be used with the disposable hygiene device, hygiene stations that include rotatable, extendable and height adjustable bathroom fixtures, and hygiene stations have a common connection point for inputs and outputs.

Abstract: A tool is described to aid in the design and verification of multi-input, multi-output power supply systems. The designer describes the system requirements and constraints to the tool, which allows an iterative exploration of various alternative designs that satisfy the requirements and constraints. Alternative designs may comprise different power supply topologies, multiple controllers or multi-controllers, or configurable controllers that implement the power supply system. The tool generates a design for a power supply system that is reconfigurable to allow for performance optimization. The power supply system is configurable automatically according to a digital control signal. The digital control signal comprises configuration data which establishes the structure of the power supply system, and which determines the output power conditions of the power source.

Abstract: A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.