Abstract: A system for providing high resolution image output for pilotage and two color operation for threat detection is disclosed. The system comprises a focal plane array comprising a plurality of pixels arranged into groups of equal numbers, wherein each pixel comprises at least two detectors for receiving electromagnetic energy and a readout integrated circuit.

Abstract: Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).

Abstract: A system for providing high resolution image output for pilotage and two color operation for threat detection, the system comprising a focal plane array, the focal plane array comprising: a plurality of pixels, wherein the pixels are arranged into groups of equal numbers of pixels, each pixel comprising: at least two detectors configured to receive electromagnetic energy; and a readout integrated circuit comprising an analog portion and a digital portion, which combine to form a current to frequency conversion circuit configured to convert current received from one of the at least two detectors into a pulse train, and a counter in operative communication with the frequency conversion circuit configured to count pulses in the pulse train during an integration time, wherein each detector from each of the pixels in a group of pixels is configured such that it can be connected to or disconnected from at least one detector from each adjacent pixel in a row or column from the same said group of pixels, and wherein

Abstract: Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.

Abstract: A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

Abstract: Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).

Abstract: Methods and systems for enabling an approximation of true snapshot integration by lowering total power requirements, total detector bias current, integrated charge per detector and detector impedance while allowing for higher ROIC input noise through the use of microbolometer photodetectors, super-pixels, and techniques for their use are herein provided.

Abstract: A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

Abstract: Techniques and architectures for simultaneous readout and integration of image data from pixels while increasing their sensitivity and reducing required data rates for moving information off of the chip using pixels configured to conduct Analog-to-Digital Conversions (ADCs) of image data, wherein each pixel operates in a rolling Integrate While Read (IWR) mode using SRAM in place of traditional latches for in-pixel storage.

Abstract: An integration circuit having multiple wells that allow for the simultaneous storage of charge during an integration interval and techniques for using the same provide benefits in dynamic range that enhance the performance of pixels. The circuit and techniques described herein could also be used in many different infrared focal plane array applications where higher dynamic range is desired and multiple gain state outputs are allowed.

Abstract: An integration circuit having multiple wells that allow for the simultaneous storage of charge during an integration interval and techniques for using the same provide benefits in dynamic range that enhance the performance of pixels. The circuit and techniques described herein could also be used in many different infrared focal plane array applications where higher dynamic range is desired and multiple gain state outputs are allowed.

Abstract: Methods and systems for enabling an approximation of true snapshot integration by lowering total power requirements, total detector bias current, integrated charge per detector and detector impedance while allowing for higher ROIC input noise through the use of microbolometer photodetectors, super-pixels, and techniques for their use are herein provided.

Abstract: A system and method is provided for analog to digital conversion, the system having: a front end whereby a current is converted to digital pulses; and a back end with a coarse conversion unit outputting a pulse count; and a fine conversion unit outputting a count time measurement count; wherein said back end unit is configured to combine said pulse count and said count time measurement to produce a high dynamic range output, said output being the product of the one more than the pulse count and the integration time divided by the sum of the integration time and the count time management count.

Abstract: A high density, high speed ROIC uses in-pixel integration capacitors and comparators to convert each pixel charge to a train of pulse spikes which increment a capacitor to successive, discrete charge values that represent a digital, non-binary count value of an in-pixel multi-value digital counter (MVDC). The MVDC can include a plurality of stages whereby comparators limit the maximum count of each stage and increment subsequent stages. The maximum count can be a power of two for subsequent direct ADC conversion to binary. The count values and the residual integration capacitor charge can be read out by ramping the comparator reference inputs and measuring the comparator output timings, effectively forming partially in-pixel single-slope ADC's. The comparators can include temporary internal positive feedback to maintain consistency of the spike pulses to better than 10%.

Abstract: The invention measures the frequency of a heterodyne laser radar (LADAR) system signal in the input cell of a focal plane array (FPA). Embodiments amplify the return signal, and drive it into a counter for a fixed period of time. The frequency is the number of counts divided by the count time. An example design amplifier amplifies the return of a single photon response of an avalanche photodiode with a gain of 100 into a digital signal level at a 200 MHz rate with only 84 ?W, demonstrating the feasibility of the approach.

Abstract: A compact signal averaging circuit having an input, a first switch operatively connected to the input, a second switch operatively connected to the first switch, wherein the first switch is coupled to the circuit between the input and the second switch, a first FET having a gate, a source and a drain, wherein the gate is operatively connected to the circuit between the first switch and the second switch, a second FET comprising a gate, a source and a drain, wherein the source is operatively connected to a voltage supply and to the second switch, and an output operatively connected to the first FET drain and the second FET drain.

Abstract: The invention measures the frequency of a heterodyne laser radar (LADAR) system signal in the input cell of a focal plane array (FPA). Embodiments amplify the return signal, and drive it into a counter for a fixed period of time. The frequency is the number of counts divided by the count time. An example design amplifier amplifies the return of a single photon response of an avalanche photodiode with a gain of 100 into a digital signal level at a 200 MHz rate with only 84 ?W, demonstrating the feasibility of the approach.

Abstract: An imaging system configured with readout circuit redundancy is disclosed. Pixel data from a particular column can be steered around a defective readout circuit to an operational readout circuit. Thus, larger imaging arrays which are generally more prone to common column circuitry defects are enabled. In addition, imaging systems configured with significant on-chip signal processing, which are also more prone to common column circuitry defects, are enabled. The occurrence of lost pixel data from an entire column is eliminated or otherwise reduced, thereby increasing overall operability and yield of the imaging system. The system can be implemented on a single chip or a chip set.

Abstract: Described techniques extend (e.g., by a factor of 2) the dynamic range of voltage swing for amplifiers and other integrated circuits (e.g., buffers) that are fabricated using lower voltage rated semiconductor processes. Such processes include, for instance, thin gate oxide MOS, and other semiconductor processes that provide desirable features that are typically not associated with high voltage processes, such as increased radiation hardness, higher speed logic, and compactness. Thus, relatively large dynamic range is enabled for integrated circuits fabricated using feature-rich lower voltage rated semiconductor processes.

Abstract: Techniques for precise removal of offset charge associated with the reset switch of an integration circuit are disclosed. Offset cancellation circuitry includes a single reset offset subtraction circuit and a replica integrator, which is configured identically to the integrators to be offset cancelled. An offset charge is generated by the circuitry and capacitively coupled to the target integrators. This generated offset charge causes voltage at the input node of each target integrator to substantially match the desired starting voltage level of the targeted integration process. Minimal additional space and circuitry is needed. All of the undesired offset charge is cancelled, without canceling any of the desired input current.