Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

Abstract: An electrochemical acrylonitrile sensor comprises a housing, an electrolyte disposed within the housing, and a plurality of electrodes in contact with the electrolyte within the housing. The plurality of electrodes comprises a working electrode and a counter electrode. The electrodes comprise a catalytic material, which may comprise gold. A potential is applied between the counter electrode and the working electrode.

Abstract: Peptide vaccine that is a mixture of different peptide species, where each species has a number of fixed amino acid residues and a number of randomized residues. The fixed resides are the same amino acid residues at the corresponding positions in each species of the mixture while the randomized residues are randomly any available candidate amino acids chosen by design. The degree of randomization may be also been chosen according to the design under a particular situation. This type of peptide vaccines have shown to be able to induce highly specific antibodies against epitopes that are otherwise difficult to induce antibodies in vitro, for example the GPG triplet in the V3 of HIV-1 gp120.

Abstract: An electrochemical acrylonitrile sensor comprises a housing, an electrolyte disposed within the housing, and a plurality of electrodes in contact with the electrolyte within the housing. The plurality of electrodes comprises a working electrode and a counter electrode. The electrodes comprise a catalytic material, which may comprise gold. A potential is applied between the counter electrode and the working electrode.

Abstract: A semiconductor bullet lot dispatch system is provided. The semiconductor bullet lot dispatch system includes a plurality of lots having bullet lots and non-bullet lots, and a processing site having a plurality of load ports used to run the lots. The semiconductor bullet lot dispatch system also includes a bullet lot arriving time initial module configured to collect work flow information of the lots and calculate bullet lot arriving time intervals; and a port remaining time initial module configured to calculate port next available time intervals. Further, the semiconductor bullet lot dispatch system includes a future constraint check module configured to match the bullet lots with the load ports, and a bullet lot scenario engine module configured to calculate a total available lot count of each of available load ports and dispatch the bullet lots to the load ports.

Abstract: A system comprising a software application which can be installed on communications devices to create a social network where users can share the contents of their real closet and their aspirational closet including vendor item combined with a means for vendors to tap into said social network and suggest combinations of clothing and accessories including items for purchase to complete the look.

Abstract: A semiconductor bullet lot dispatch system is provided. The semiconductor bullet lot dispatch system includes a plurality of lots having bullet lots and non-bullet lots, and a processing site having a plurality of load ports used to run the lots. The semiconductor bullet lot dispatch system also includes a bullet lot arriving time initial module configured to collect work flow information of the lots and calculate bullet lot arriving time intervals; and a port remaining time initial module configured to calculate port next available time intervals. Further, the semiconductor bullet lot dispatch system includes a future constraint check module configured to match the bullet lots with the load ports, and a bullet lot scenario engine module configured to calculate a total available lot count of each of available load ports and dispatch the bullet lots to the load ports.

Abstract: Peptide vaccine that is a mixture of different peptide species, where each species has a number of fixed amino acid residues and a number of randomized residues. The fixed resides are the same amino acid residues at the corresponding positions in each species of the mixture while the randomized residues are randomly any available candidate amino acids chosen by design. The degree of randomization may be also been chosen according to the design under a particular situation. This type of peptide vaccines have shown to be able to induce highly specific antibodies against epitopes that are otherwise difficult to induce antibodies in vitro, for example the GPG triplet in the V3 of HIV-1 gp120.

Abstract: A device that can electronically track operator ground connectivity to; a) provide continuous visual and/or auditory indication of connection state, b) optionally provide that the ground connectivity state may be monitored and displayed remotely using RF communications, and c) optionally provide that the operators device can track RFID ‘follower’ tags specifically placed to facilitate work-flow data recording and the correlation of the operators activities with specific work-flow process.

Abstract: A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.

Abstract: Gate level netlists used for timing analysis in integrated circuit design are reduced using a timing shell generator while preserving critical information for timing analysis. After verification of timings, the gate level netlist is convened into a shell containing block boundary information. The function of the shell generator is to delete internal cells meeting a set of criteria. The result is a shell netlist containing a subset of the original netlist. Thus, the design cycle time involved and computing time and resources needed in ASIC development for chips using circuits represented by timing shell netlists are decreased by substituting design verification at the top level of large hierarchical netlists or large flat netlists by bottom up verification procedures using timing shells.

Abstract: Digital video signals are adaptively compressed for communication to a receiver. Superblocks, each containing a plurality of blocks of digital video data, are compressed using PCM, DPCM with a general motion vector for the entire superblock, and DPCM with a specific motion vector for each block contained within a superblock. The result of each compression mode is compared after accounting for overhead data, to determine which results in the least amount of data for each block. These blocks are assembled into a superblock, and compared together with necessary overhead and motion vector data to the same superblock processed using all PCM as well as the superblock processed using all DPCM. The comparison determines which compression mode produces the least amount of data for the superblock. The most compact superblock is selected for transmission.

Abstract: A two stage accumulator is provided for updating coefficients. The accumulator is particularly useful in an adaptive equalizer. A first stage of the accumulator receives an error word and outputs sign and carry bits resulting from the addition of the error word and an N-bit LSB portion of a larger M-bit coefficient. A second stage is responsive to the sign and carry bits for updating the (M-N) MSB's of the M-bit coefficient. New error words are cyclically provided to the first stage during successive coefficient update cycles. The first stage can be implemented using an N-bit twos complement adder. The second stage can be implemented using an up/down counter. A leakage function is provided by causing the up/down counter to periodically skip over increment and decrement cycles.

Abstract: Convergence of a complex adaptive equalizer used in digital communications is substantially improved by updating all coefficients of the equalizer during each filter clock cycle. Complex signal data is passed through a plurality of successive delay stages to provide N sets of delayed complex signal data. The product of each set and a complex error signal is obtained. Each product is concurrently updated with previous product data for the set to provide N sets of updated complex coefficients for selective input to equalizer filters. In an illustrated embodiment, the updated coefficients are truncated and their gain is adjusted prior to input to the filters. The updated coefficients can be multiplexed to provide a clocked stream of coefficient sets for input to the equalizer filters. A VLSI implementation of the equalizer is also disclosed.