Abstract: Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes scan chains with scan cells interspersed throughout the core circuitry. The scan control circuitry controls the scan test circuitry to scan test the core circuitry. The debug control circuitry utilizes the scan test circuitry and controls the scan control circuitry to debug failure conditions of the integrated circuit during normal use. The scan control circuitry applies a debug clock signal to a clock port of each scan cell of a given scan chain to store data values that are generated by the core circuitry into the scan cells. The scan control circuitry controls the scan test circuitry to scan shift out the stored data values generated by the core circuitry during the debug process.