Patents by Inventor Allis Chen
Allis Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6590269Abstract: A package structure for a photosensitive chip includes a substrate having an upper surface and a lower surface, and a frame layer having a first surface and a second surface. The frame layer is formed on the substrate by way of injection molding with the first surface contacting the upper surface. A cavity is formed between the substrate and the frame layer. The second surface is formed with a depression in which plural projections each having a suitable height are formed. The frame layer is formed directly on the substrate by way of injection molding. The package structure further includes a photosensitive chip arranged within the cavity, a plurality of wires for connecting the substrate to the photosensitive chip, and a transparent layer rested on the projections within the depression. Accordingly, the yield can be improved and the manufacturing processes can be facilitated.Type: GrantFiled: April 1, 2002Date of Patent: July 8, 2003Assignee: Kingpak Technology Inc.Inventors: Jason Chuang, Allis Chen, Jachson Hsieh, Hsiu Wen Tu, Meng Ru Tsai, Mon Nan Ho, Fu Yung Huang, Yung Sheng Chiu, Jichen Wu, Chih Cheng Hsu
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Publication number: 20030116817Abstract: The image sensor structure of the invention is used for electrically connecting to a printed circuit board. The image sensor structure includes a substrate, a projecting layer, an image sensing chip, a plurality of wires, and a transparent layer. The substrate has a first surface and a second surface. The first surface is formed with signal output terminals for electrically connecting to the printed circuit board. The projecting layer has an upper surface and a lower surface. The lower surface is adhered to the second surface of the substrate to form a cavity with the substrate. The upper surface is formed with signal input terminals. The image sensing chip is placed within the cavity formed by the substrate and the projecting layer, and is adhered onto the second surface of the substrate. The plurality of wires each has a first terminal and a second terminal. The first terminals are electrically connected to the image sensing chip.Type: ApplicationFiled: December 20, 2001Publication date: June 26, 2003Inventors: Nai Hua Yeh, Chen Pin Peng, Jason Chuang, Hsiu Wen Tu, Kuang Yu Fan, Mon Nan Ho, Fu Yung Huang, Meng Ru Tsai, Allis Chen, Chih Hsien Chung, Chih Cheng Hsu, Yung Sheng Chiu
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Publication number: 20030118680Abstract: A jig structure for an integrated circuit package. The jig structure is used for integrated circuits to be covered by glue. The jig structure includes a base formed with a plurality of receiving regions for receiving the integrated circuits, a mold plate covering the base, a plurality of glue inlets formed on the mold plate at locations corresponding to each receiving region on the base, and a projection arranged between each glue inlet and its corresponding receiving region. The projection blocks and buffers the glue entering the receiving regions from the glue inlets. According to the jig structure, the mold flow of the glue can be effectively buffered when the glue is poured. Thus, it is not necessary to redesign the jig with the change of the relative position relationships between the glue inlets and the integrated circuits. The jig of this invention can be widely used for packaging various integrated circuits having different sizes and specifications.Type: ApplicationFiled: December 20, 2001Publication date: June 26, 2003Inventors: Chief Lin, C. S. Cheng, Allis Chen
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Patent number: 6565008Abstract: A manufacturing method of a module card comprises steps of: providing a base board having a golden finger; mounting a chip on the base board for electrically connecting to the golden finger; and forming a packing layer on the chip for forming the module card. A module card comprises: a base board; a chip mounting on a surface of the base board; a golden finger on the board and electrically connecting to the chip; and a packing layer forming on the chip for covering the chip.Type: GrantFiled: December 4, 2001Date of Patent: May 20, 2003Assignee: Kingpak Technology Inc.Inventors: Mon Nan Ho, Hsiu Wen Tu, Kuo Feng Feng, Yung Sheng Chiu, Joe Liu, Nai Hua Yeh, Wen Chuan Chen, Allis Chen
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Publication number: 20030071129Abstract: A manufacturing method of a module card comprises steps of: providing a base board having a golden finger; mounting a chip on the base board for electrically connecting to the golden finger; and forming a packing layer on the chip for forming the module card. A module card comprises: a base board; a chip mounting on a surface of the base board; a golden finger on the board and electrically connecting to the chip; and a packing layer forming on the chip for covering the chip.Type: ApplicationFiled: December 4, 2001Publication date: April 17, 2003Inventors: Mon Nan Ho, Hsiu Wen Tu, Kuo Feng Feng, Yung Sheng Chiu, Joe Liu, Nai Hua Yeh, Wen Chuan Chen, Allis Chen
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Patent number: 6501187Abstract: A semiconductor package structure having central leads according to the invention includes a substrate, a semiconductor device, a plurality of wires, and glue. A long slot penetrating through the substrate is formed in the substrate. A plurality of bonding pads formed on the semiconductor device are mounted on substrate. The plurality of bonding pads on the semiconductor device are exposed via the long slot of the substrate. The length of the semiconductor device is smaller than that of the long slot of the substrate so that a channel is formed at one side of the long slot when the semiconductor device is mounted on the substrate. The plurality of wires are arranged within the long slot of the substrate for electrically connecting the plurality of bonding pads on the semiconductor device to the plurality of signal output terminals on the substrate. The glue is provided for sealing the upper surface of the substrate to protect the semiconductor device.Type: GrantFiled: November 21, 2001Date of Patent: December 31, 2002Inventors: Nai Hua Yeh, Chen Pin Peng, Chief Lin, Ching-Shui Cheng, Allis Chen
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Patent number: 6489572Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.Type: GrantFiled: January 23, 2001Date of Patent: December 3, 2002Assignee: Kingpak Technology Inc.Inventors: Mon Nan Ho, Chih-Hong Chen, Yen Cheng Huang, Li Huan Chen, Kuo Feng Peng, Jichen Wu, Allis Chen, Wen Chuan Chen
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Publication number: 20020096751Abstract: An integrated circuit structure having an adhesive agent for adhering to a substrate includes a first surface and a second surface opposite to the first surface. The first surface is formed with a plurality of bonding pads for electrically connecting to the substrate and transmitting signals from the integrated circuit to the substrate. An adhesive agent, which is non-adhesive at the room temperature, is applied onto the second surface. The adhesive agent becomes adhesive under pressing/heating so as to adhere onto the substrate. According to the structure, the problems caused by the overflowed glue can be avoided, the manufacturing processes can be facilitated, and the yield can be improved.Type: ApplicationFiled: January 24, 2001Publication date: July 25, 2002Inventors: Wen Chuan Chen, Kuo Feng Peng, C. H. Chou, Allis Chen, Nai Hua Yeh, Wu Hsiang Lee, Meng Ru Tsai, Hsiu Wen Tu, Jichen Wu
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Publication number: 20020096762Abstract: A structure of stacked integrated circuits for mounting on a circuit board includes a substrate, a lower integrated circuit, a plurality of wirings, a plurality of metallic balls, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals and a second surface formed with signal output terminals for electrically connecting to the circuit board. The lower integrated circuit has a first surface adhered to the first surface of the substrate and a second surface formed with a plurality of bonding pads. Each of the wirings has a first end and a second end away from the first end. The first ends are electrically connected to the bonding pads of the lower integrated circuit. The second ends are electrically connected to the signal input terminals on the first surface of the substrate. The plurality of metallic balls are formed on the second surface of the lower integrated circuit.Type: ApplicationFiled: January 24, 2001Publication date: July 25, 2002Inventors: Wen Chuan Chen, Kuo Feng Peng, C. H. Chou, Allis Chen, Nai Hua Yeh, Yen Cheng Huang, Fu Yung Huang, Chief Lin, C. S. Cheng
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Publication number: 20020096761Abstract: A structure of stacked integrated circuits arranged on a circuit board includes a substrate, a lower integrated circuit, a plurality of wirings, a passivation layer, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals, and a second surface formed with signal output terminals for electrically connecting to the circuit board. The lower integrated circuit has a first surface and a second surface. The first surface of the lower integrated circuit is adhered onto the first surface of the substrate. The second surface of the lower integrated circuit is formed with a plurality of bonding pads. The wirings each includes a first end and a second end opposite to the first end. The first ends of the wirings are electrically connected to the bonding pads of the lower integrated circuit, and the second ends of the wirings are electrically connected to the signal input terminals of the substrate, respectively.Type: ApplicationFiled: January 24, 2001Publication date: July 25, 2002Inventors: Wen Chuan Chen, Kuo Feng Peng, C. H. Chou, Allis Chen, Nai Hua Yeh, Yen Cheng Huang, Fu Yung Huang, Chief Lin, C. S. Cheng
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Publication number: 20020096360Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.Type: ApplicationFiled: January 23, 2001Publication date: July 25, 2002Inventors: Mon Nan Ho, C. H. Chen, Yen Cheng Huang, Li Huan Chen, Kuo Feng Peng, Jichen Wu, Allis Chen, Wen Chuan Chen
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Publication number: 20020096754Abstract: A stacked structure of integrated circuits for electrically connecting to a circuit board includes a substrate, a lower integrated circuit, a plurality of wirings, and an upper integrated circuit. The lower integrated circuit has a lower surface and an upper surface. The lower surface is adhered onto the first surface of the substrate. A plurality of bonding pads are formed on the upper surface. The wirings each has a first end and a second end. The first ends of the wirings are electrically connected to the bonding pads of the lower integrated circuit. The second ends of the wirings are electrically connected to the signal input terminals of the substrate. The upper integrated circuit has a lower surface and an upper surface. Two recesses are formed at two sides of the lower surface. The upper integrated circuit is adhered to the upper surface of the lower integrated circuit so as to stack above the lower integrated circuit.Type: ApplicationFiled: January 24, 2001Publication date: July 25, 2002Inventors: Wen Chuan Chen, Kuo Feng Peng, C. H. Chou, Allis Chen, Nai Hua Yeh, Yen Cheng Huang, C. F. Wang, Chen Pin Peng, Wen Tsan Lee, Jichen Wu
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Publication number: 20020096766Abstract: A package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The second surface is formed with a plurality of signal output terminals for electrically connecting to the circuit board. The integrated circuit has a lower surface and an upper surface. Recesses are formed at two sides of the lower surface, and a plurality of bonding pads are formed on the upper surface. The adhesive layer is used for adhering the lower surface of the integrated circuit to the first surface of the substrate. The wirings are electrically connecting to the bonding pads of the integrated circuit and to the signal input terminals of the substrate. The glue layer is used for sealing the plurality of wirings and the integrated circuits.Type: ApplicationFiled: January 24, 2001Publication date: July 25, 2002Inventors: Wen Chuan Chen, Kuo Feng Peng, C. H. Chou, Allis Chen, Nai Hua Yeh, Yen Cheng Huang, C. F. Wang, Chen Pin Peng, Wen Tsan Lee, Jichen Wu