Patents by Inventor Allison YAU

Allison YAU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230420245
    Abstract: In one example, a process chamber comprises a lid assembly, a first gas supply, second gas supply, a chamber body, and a substrate support. The lid assembly comprises a gas box, a gas conduit passing through the gas box, a blocker plate, and a showerhead. The gas box comprises a gas distribution plenum, and a distribution plate comprising a plurality of holes aligned with the gas distribution plenum. The blocker plate is coupled to the gas box forming a first plenum. The showerhead is coupled to the blocker plate forming a second plenum. The first gas supply is coupled to the gas distribution plenum, and the second gas supply system is coupled to the gas conduit. The chamber body is coupled to the showerhead, and the substrate support assembly is disposed within an interior volume of the chamber body, and is configured to support a substrate during processing.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Daemian Raj BENJAMIN RAJ, Gregory Eugene CHICHKANOFF, Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Abhigyan KESHRI, Allison YAU
  • Publication number: 20230411462
    Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Sang-Jin Kim, Zeqiong Zhao, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Patent number: 11798803
    Abstract: In one example, a process chamber comprises a lid assembly, a first gas supply, second gas supply, a chamber body, and a substrate support. The lid assembly comprises a gas box, a gas conduit passing through the gas box, a blocker plate, and a showerhead. The gas box comprises a gas distribution plenum, and a distribution plate comprising a plurality of holes aligned with the gas distribution plenum. The blocker plate is coupled to the gas box forming a first plenum. The showerhead is coupled to the blocker plate forming a second plenum. The first gas supply is coupled to the gas distribution plenum, and the second gas supply system is coupled to the gas conduit. The chamber body is coupled to the showerhead, and the substrate support assembly is disposed within an interior volume of the chamber body, and is configured to support a substrate during processing.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Daemian Raj Benjamin Raj, Gregory Eugene Chichkanoff, Shailendra Srivastava, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Abhigyan Keshri, Allison Yau
  • Patent number: 11784229
    Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 10, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Sang-Jin Kim, Zeqiong Zhao, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Publication number: 20230274968
    Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Zeqiong Zhao, Sang-Jin Kim, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Patent number: 11646216
    Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: May 9, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Zeqiong Zhao, Sang-Jin Kim, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Patent number: 11538677
    Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: December 27, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Chuanxi Yang, Hang Yu, Yu Yang, Chuan Ying Wang, Allison Yau, Xinhai Han, Sanjay G. Kamath, Deenesh Padhi
  • Publication number: 20220336216
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the inert gas. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The processing region may be maintained free of helium delivery during the deposition method.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 20, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Zeqiong Zhao, Allison Yau, Sang-Jin Kim, Akhil Singhal, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Publication number: 20220122872
    Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Zeqiong Zhao, Sang-Jin Kim, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Publication number: 20220123114
    Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Sang-Jin Kim, Zeqiong Zhao, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Publication number: 20220068630
    Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 3, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Chuanxi Yang, Hang Yu, Yu Yang, Chuan Ying Wang, Allison Yau, Xinhai Han, Sanjay G. Kamath, Deenesh Padhi
  • Publication number: 20200365386
    Abstract: In one example, a process chamber comprises a lid assembly, a first gas supply, second gas supply, a chamber body, and a substrate support. The lid assembly comprises a gas box, a gas conduit passing through the gas box, a blocker plate, and a showerhead. The gas box comprises a gas distribution plenum, and a distribution plate comprising a plurality of holes aligned with the gas distribution plenum. The blocker plate is coupled to the gas box forming a first plenum. The showerhead is coupled to the blocker plate forming a second plenum. The first gas supply is coupled to the gas distribution plenum, and the second gas supply system is coupled to the gas conduit. The chamber body is coupled to the showerhead, and the substrate support assembly is disposed within an interior volume of the chamber body, and is configured to support a substrate during processing.
    Type: Application
    Filed: April 9, 2020
    Publication date: November 19, 2020
    Inventors: Daemian Raj BENJAMIN RAJ, Gregory Eugene CHICHKANOFF, Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Abhigyan KESHRI, Allison YAU