Abstract: A computer-implemented method and apparatus for generating questions. The method comprises receiving a rule; dynamically generating a graph representing a question, the graph comprising one or more nodes, each node associated with a rule having one or more variables; sampling a value from the value domain for the variable; and synthesizing a textual representation of the graph.

Abstract: Device, system and method of modeling homogeneous information. For example, a method that includes providing to a model-based application an input model including a refinable homogeneous record having a base type, wherein said homogeneous record is defined with a homogeneous constraint to only include data members of a type compatible with the base type. The homogeneous record is defined in a modeling environment that is able to automatically enforce the homogeneous constraint for the homogeneous record and for refinements thereof.

Abstract: A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.

Abstract: A computer-implemented method and apparatus for fabricating data for database applications. The method comprises intercepting a command issued by an application, the command being addressed to a database; formulating a problem in accordance with the command; obtaining a solution for the problem, the solution comprising fabricated data; providing a second command for updating the database with the fabricated data; and providing the command to the database, whereby a response from the database based on the fabricated data is provided to the application.

Abstract: A method for compliance testing of a circuit design that includes at least one processor and a memory includes defining a memory model. The memory model includes synchronization mechanisms for synchronizing access to the memory by software instructions in different program threads running on the at least one processor. Synchronization-related parameters, which are applicable to at least one sequence of the software instructions in the different program threads, are specified. A coverage model is defined as a multi-dimensional cross-product of values of the synchronization-related parameters. At least one test program is generated using the coverage model, and a compliance of the design with the memory model is tested by subjecting the design to the at least one test program.

Abstract: Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

Abstract: An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.

Abstract: Generating a number based on a bitset constraints. For example, a method of generating a pseudo random number satisfying a bitset constraint may include determining a number of possible solutions satisfying the bitset constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo-random number based on the index. Other embodiments are described and claimed.

Abstract: A parametrically controlled model-based test generator automatically generates architectural compliance test suites for different implementations of a processor architecture, based on a set of architectural decisions chosen among optional behaviors for each implementation. Thus, different implementations of the same architecture can be easily supported by modifying the parameter values. In addition, ongoing changes to the architecture or comprehensive updates to the test suite can be easily handled by updating the architecture model or the coverage models, forgoing the need to review the whole, potentially huge, set of tests.

Abstract: A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.

Abstract: An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Abstract: A design verification system that verifies the operation of multi-processor architecture by generating test programs in which the behavior of the processor, when executing the test program, is evaluated against the behavior required by the design specification. The test program generator produces scenarios for a multi-processor design in which non-unique results may occur. The system is provided with facilities to report expected outcomes, and to evaluate the validity of non-unique results in multiple resources under conditions of non-unique result propagation and dependencies among adjacent and non-adjacent resources.

Abstract: Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

Abstract: A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path.

Abstract: Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.

Abstract: A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.

Abstract: Converting a mask constraint into a bitset constraint. For example, a method of converting a mask constraint into a bitset constraint may include determining an intermediate bitset based on a variable-bit component of the mask constraint; and generating the bitset constraint based on the intermediate bitset and on a fixed-bit component of the mask constraint. Other embodiments are described and claimed.

Abstract: Generating a number based on a bitset constraints. For example, a method of generating a pseudo random number satisfying a bitset constraint may include determining a number of possible solutions satisfying the bitset constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo-random number based on the index. Other embodiments are described and claimed.

Abstract: Converting a mask constraint into a bitset constraint. For example, a method of converting a mask constraint into a bitset constraint may include determining an intermediate bitset based on a variable-bit component of the mask constraint; and generating the bitset constraint based on the intermediate bitset and on a fixed-bit component of the mask constraint. Other embodiments are described and claimed.

Abstract: Apparatus for automatically generating test programs is provided. The apparatus includes a test generator, which is adapted to receive a description of a system under test, expressed in terms of variables associated with the system and conditional constraints including semantics applied to the variables, to receive a definition of an event to be tested in the system, to generate an ECondCSP over the variables responsively to the definition of the event and to the conditional constraints, such that at least some of the semantics of the conditional constraints are preserved in the ECondCSP when one or more of the variables to which the semantics are applied are inactive, and to solve the ECondCSP to generate a test case for the system.