Abstract: A design for test (DFT) block of a system on a chip (SOC) includes a function mapping interface coupled to a set of function interfaces of an intellectual property (IP) block core; and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interposer to manage assignments of the plurality of test interfaces from the function mapping interface to a plurality of placeholder interfaces of a collar, wherein the function mapping interface maps the set of function interfaces to the plurality of test interfaces.