Patents by Inventor Alma Anderson

Alma Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791817
    Abstract: Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 17, 2023
    Assignee: NXP USA, Inc.
    Inventor: Alma Anderson
  • Publication number: 20230047185
    Abstract: Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.
    Type: Application
    Filed: August 10, 2021
    Publication date: February 16, 2023
    Inventor: Alma Anderson
  • Patent number: 11575258
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: February 7, 2023
    Assignee: NXP B.V.
    Inventor: Alma Anderson
  • Publication number: 20210391714
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventor: Alma ANDERSON
  • Publication number: 20200161986
    Abstract: A low voltage drop rectifier is provided. The rectifier includes a diode having a first terminal coupled at an input node and a second terminal coupled at an output node. A first transistor having a first current electrode is coupled at the input node and a second current electrode is coupled at the output node. A comparator having a first input is coupled at the input node, a second input is coupled at the output node, and an output is coupled to a control electrode of the first transistor. A bias circuit is coupled to the comparator circuit and is configured to generate a bias current in the comparator.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Xueyang Geng, Madan Mohan Reddy Vemula, Alma Anderson
  • Publication number: 20190235559
    Abstract: A startup circuit for a voltage reference circuit is provided. The startup circuit includes first, second, and third transistors. The first transistor has a first current electrode coupled to the voltage reference circuit, a control electrode, and a second current electrode coupled to a ground terminal. The second transistor has a first current electrode and a control electrode both coupled to a power supply voltage terminal, and a second current electrode. The third transistor has a first current electrode coupled to the second current electrode of the second transistor and to the control electrode of the first transistor, a control electrode coupled to the voltage reference circuit, and a second current electrode coupled to the ground terminal. During application of a power supply voltage, the second transistor is off, thus providing only a leakage current to the gate of the first transistor. This provides for reliable startup with very low residual current after startup is complete.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Ahmad Dashtestani, Alma Anderson
  • Patent number: 9231589
    Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: January 5, 2016
    Assignee: NXP B.V.
    Inventors: Hok-tung Wong, Yang Zhao, Brad Gunter, Alma Anderson, James Caravella
  • Patent number: 9112486
    Abstract: Aspects of the present disclosure are directed towards apparatus useful for processing communications between different signaling voltage levels. Different signaling voltage levels are accomplished by creating true and complement signals from at least one input signal, each of which are subject to different delays, and level shifting the true and complement signals to a new signaling voltage level. The true or complement signal subject to a smaller timing delay is selected, and used to provide an output signal.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: August 18, 2015
    Assignee: NXP B.V.
    Inventor: Alma Anderson
  • Publication number: 20140347111
    Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.
    Type: Application
    Filed: December 11, 2013
    Publication date: November 27, 2014
    Applicant: NXP B.V.
    Inventors: Hok-tung Wong, Yang Zhao, Brad Gunter, Alma Anderson, James Caravella
  • Publication number: 20140055186
    Abstract: Aspects of the present disclosure are directed towards apparatus useful for processing communications between different signaling voltage levels. Different signaling voltage levels are accomplished by creating true and complement signals from at least one input signal, each of which are subject to different delays, and level shifting the true and complement signals to a new signaling voltage level. The true or complement signal subject to a smaller timing delay is selected, and used to provide an output signal.
    Type: Application
    Filed: November 15, 2012
    Publication date: February 27, 2014
    Applicant: NXP B.V.
    Inventor: Alma Anderson
  • Patent number: 7990081
    Abstract: Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: August 2, 2011
    Assignee: NXP B.V.
    Inventors: Manoj Chandran, Alma Anderson
  • Patent number: 7979597
    Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: July 12, 2011
    Assignee: NXP B.V.
    Inventors: Amrita Deshpande, Alma Anderson, Jean-Marc Irazabal, Stephen Blozis, Paul Boogaards
  • Patent number: 7940102
    Abstract: Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 10, 2011
    Assignee: NXP B.V.
    Inventors: Alma Anderson, Joseph Rutkowski, Dave Oehler
  • Patent number: 7934034
    Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: April 26, 2011
    Assignee: NXP B.V.
    Inventors: Amrita Deshpande, Alma Anderson, Jean-Marc Irazabal, Stephen Blozis, Paul Boogaards
  • Patent number: 7859314
    Abstract: Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.
    Type: Grant
    Filed: March 31, 2007
    Date of Patent: December 28, 2010
    Assignee: NXP B.V.
    Inventors: Joseph Rutkowski, Alma Anderson
  • Publication number: 20100264970
    Abstract: Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.
    Type: Application
    Filed: April 30, 2010
    Publication date: October 21, 2010
    Applicant: NXP B.V.
    Inventors: Alma ANDERSON, Joseph RUTKOWSKI, Dave OEHLER
  • Publication number: 20100237919
    Abstract: Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.
    Type: Application
    Filed: March 31, 2007
    Publication date: September 23, 2010
    Applicant: NXP B.V.
    Inventors: Joseph Rutkowski, Alma Anderson
  • Patent number: 7788431
    Abstract: Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: August 31, 2010
    Assignee: NXP B.V.
    Inventors: Amrita Deshpande, Alma Anderson, Jean-Marc Irazabal
  • Publication number: 20100217903
    Abstract: Consistent with one example embodiment, communications systems (100,300), using a serial data transfer bus having a serial data line (110) and a clock line (120) used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers (331-338). The communications system includes a slave device (320) having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.
    Type: Application
    Filed: April 29, 2010
    Publication date: August 26, 2010
    Inventors: Amrita DESHPANDE, Alma Anderson, Jean-Marc Irazabal, Stephen Blozis, Paul Boogaards
  • Publication number: 20100205326
    Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.
    Type: Application
    Filed: April 16, 2010
    Publication date: August 12, 2010
    Applicant: NXP B.V.
    Inventors: Amrita DESHPANDE, Alma Anderson, Jean-Marc Irazabal, Stephen Blozis, Paul Boogaards