Abstract: A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.

Abstract: A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: A data flow management system and method in which an application and its clients are made aware of the available credits for each type of transfer before the transfer is attempted. This enables the clients to transmit packets only when the RX side has issued a sufficient number of credits to insure that the transmission will not be stalled. The invention eliminates the need for FIFO buffers in the PCI-Express core, since the application will not transmit packets to the core until the required number of credits for the particular transfer type is available. Therefore, packet transmissions do not require buffering in the core, as they are only sent when they can be sent all the way through the core to the link.

Abstract: A data flow management system and method in which the application and its clients are made aware of the available credits for each type of transfer before the transfer is attempted. This enables the clients to transmit packets only when the RX side has issued a sufficient number of credits to insure that the transmission will not be stalled. The invention eliminates the need for FIFO buffers in the PCI-Express core, since the application will not transmit packets to the core until the required number of credits for the particular transfer type is available. Therefore, packet transmissions do not require buffering in the core, as they are only sent when they can be sent all the way through the core to the link.

Abstract: A data packet routing mechanism including a plurality of clients for issuing read requests to a host device, the read requests each including a TAG field for identifying which of the plurality of clients issued a particular read request, wherein a completion response corresponding to the particular read request, including the TAG field, is issued from the host to the client that sent the read request, the plurality of clients being organized into M groups, each group including a predetermined number of clients; a first level routing device having an input for receiving completion responses from the host and a plurality of outputs for transmitting completion responses; and a plurality of second level routing devices, each being coupled to the plurality of clients in one of the M groups, and having an input for receiving completion responses from the first level routing device and a plurality of outputs, each output for transmitting completion responses to one of the plurality of clients in the group.

Abstract: A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

Abstract: A system for transferring data packets between a data packet transfer core and a number of clients of an application layer, including an interface between the data packet transfer core and the application layer for transferring data packets from the packet transfer core to a first client and a second client. The data packet transfer core includes a number of core buffers for receiving data packet transfers input to the data packet transfer core. Each of the number of core buffers include a cut-through data path including a register and a bypass data path, the bypass data path transferring data packets from an input to the register to an output of the register without passing through the register.

Abstract: A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.

Abstract: A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.

Abstract: A system for controlling packet transfers includes a packet transfer core; an application layer coupled to the packet transfer core by an application interface; a buffer in the packet transfer core for receiving packets from a packet source and transferring the packets to the application layer over the application interface, the packets comprising one or more words; a register in the application layer for receiving packets from the application interface; and a client device for receiving packets transferred thereto from the register. When the client is unable to receive packets from the register, the client asserts a first wait signal to the register, causing the register to continue receiving packets from the interface and storing the packets without transferring the packets to the client.

Abstract: A system for transferring packets between a packet transfer core and an application layer device over an application layer interface includes a buffer system disposed in the packet transfer core having an input for receiving packets from a packet source; an output for transferring packets to the application layer interface; a buffer device having an input coupled to the input of the buffer system and an output; a selection device having a first input coupled to the output of the buffer device, a control input and an output coupled to the output of the buffer system; and a bypass path coupled between the input of the buffer system and a second input of the selection device. The control input of the selection device receives a first wait signal from the application layer device which is not asserted in a first mode of operation and asserted in a second mode of operation.

Abstract: A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources.