Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: The invention relates to a layer system composed of a silicon-based carrier having a single-crystal surface and of a heterostructure applied directly to the single-crystal surface of the carrier. The layer system according to the invention is characterized in that the carrier comprises a silicon substrate doped with one or more dopants, wherein the doped portion extends across at least 30% of the thickness of the doped silicon substrate and a concentration of the dopants in the doped portion of the silicon substrate is predetermined such that a corrected limiting concentration GK meets the condition of formula (1): GK = ? m = i n ? ? N dot i 1 + 5 × 10 22 ? ? cm - 3 N dot i ? ? - E A i / 0.

Abstract: A group-III-nitride based layer sequence fabricated by means of an epitaxial process on a silicon substrate, the layer sequence comprising at least one doped first group-III-nitride layer (105) having a dopant concentration larger than 1×1018 cm?3, a second group-III-nitride layer (106) having a thickness of at least 50 nm and an n-type or p-type dopant concentration of less than 5×1018 cm?3, and an active region made of a group-III-nitride semiconductor material, wherein the first group-III-nitride layer comprises at least one n-type dopant selected from the group of elements formed by germanium, tin, lead, oxygen, sulphur, selenium and tellurium or a at least one p-type dopant, and wherein the active region has a volume density of either screw-type or edge type dislocations below 5×109 mm?3.

Abstract: Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate.

Abstract: Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.

Abstract: The invention relates to nitride semiconductor component having a Group III nitride layer structure which is deposited on a substrate having a Group IV substrate surface made of a Group IV substrate material with a cubical crystal structure. The Group IV substrate surface has an elementary cell with C2 symmetry, but not with a higher rotational symmetry than C2 symmetry, when any surface reconstruction is ignored. The Group III nitride layer structure has a seeding layer of ternary or quaternary Al1-x-yInxGayN, where 0?x, y<1 and x+y?1, immediately adjacent to the Group IV substrate surface. High-quality monocrystalline growth is achieved as a result. The advantage of the invention consists in the high level of crystal quality that can be achieved, in the growth of c-, a- and m-plane GaN and above all in the ease with which the silicon substrate can be wholly or partially removed, since this is easier to do in a wet chemical process than on (111)-oriented substrates.

Abstract: The invention concerns a process and an apparatus for the production of gallium nitride or gallium aluminium nitride single crystals. It is essential for the process implementation according to the invention that the vaporisation of gallium or gallium and aluminium is effected at a temperature above the temperature of the growing crystal but at least at 1000° C. and that a gas flow comprising nitrogen gas, hydrogen gas, inert gas or a combination of said gases is passed over the surface of the metal melt in such a way that the gas flow over the surface of the metal melt prevents contact of the nitrogen precursor with the metal melt.

Abstract: The invention relates to a device and a method for the measurement of the curvature of a surface (1), which is more exact and less expensive than prior art devices. The device comprises a light source (2) for the irradiation of a light beam (3) onto the surface (1), in which a birefingent element (4) is arranged between light source (2) and surface (1), in which furthermore a detector (5) is arranged for the detection of the partial beams (6,7), that are reflected from the surface (1), and at least one main axis (17) of the birefringent element (4) is positioned with respect to the light beam (3) of the light source (2) in such a way, that the light beam (3) of the light source (2) is split up into at least two parallel beams (6,7).

Abstract: Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.

Abstract: Group III nitride layers which are grown with standard c-axis orientation have a maximum hole concentration by means of magnesium doping of around 5×1017 cm?3. This restriction of the doping results in a limitation of the possible component power. The object is to achieve a higher hole concentration and thus conductivity of the p-doped layer. This is made possible by the growth of higher index facets, which proceeds by roughening of the c-planar surface, structuring and subsequent preferentially lateral overgrowth with magnesium-doped group III nitride layers.

Abstract: Semiconductor components such as transistor components, for example, which exist on high Al-containing active layers or layers supplying charge carriers, having a new layer construction providing increased charge carrier mobility.

Abstract: The invention relates to a process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising the steps: provision of a substrate that has a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: The invention relates to a device and a method for the measurement of the curvature of a surface (1). It is the object of the present invention to provide a device for the determination of the curvature of a surface (1), that is more exact and less expensive as the devices of the prior art. Therefore the device comprises a light source (2) for the irradiation of a light beam (3) onto the surface (1), in which a birefingent element (4) is arranged between light source (2) and surface (1), in which furthermore a detector (5) is arranged for the detection of the partial beams (6,7), that are reflected at the surface (1), and at least one main axis (17) of the birefringent element (4) is positioned with respect to the light beam (3) of the light source (2) in such a way, that the light beam (3) of the light source (2) is split up into at least two parallel beams (6,7), if necessary with the help of additional optical elements.

Abstract: This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.

Abstract: The invention relates to a method for depositing thick III-V semiconductor layers on a non-III-V substrate, particularly a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor. The aim of the invention is to carry out the crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the occurrence of unfavorable lattice distortions. To this end, the invention provides that a thin intermediate layer is deposited at a reduced growth temperature between two III-V layers.