Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: In some embodiments, a meta-data inspection data store may contain hierarchical components and subcomponents of an industrial asset and define points of interest. An industrial asset inspection platform may access that information and generate an inspection plan, including an association of at least one sensor type with each of the points of interest. The platform may then store information about the inspection plan in an inspection plan data store and receive inspection data (e.g., from a manual inspection, from an inspection robot, from a fixed sensor, etc.). A smart tagging algorithm may be executed to associate at least one point of interest with an appropriate portion of the received inspection data based on information in the inspection plan data store.

Abstract: In some examples, a computing device receives, from a plurality of data sources associated with a plurality of service providers, data related to user interactions with information provided by the service providers. The computing device determines users associated with the user interactions, and determines whether the users are new users or existing users based at least on accessing a user information data structure. The computing device uses a value-determining machine learning model to determine respective values associated with the new users, and adjusts values of the received data based on the respective values. The computing device uses a plurality of data synthetization machine learning models to generate synthetic data based on the adjusted data. The computing device determines an allocation of resources at least by comparing the adjusted data and the synthetic data of the data sources with the adjusted data and synthetic data of others of the data sources.

Abstract: In some examples, a computing device may receive data from a plurality of groups of data sources. The computing device may access a plurality of data synthetization machine learning models configured for generating synthetic data. Respective ones of the data synthetization machine learning models may correspond to respective ones of the groups of data sources. The computing device generates first synthetic data by inputting, to a first data synthetization machine learning model, first data received from a first data source group, and generates second synthetic data by inputting, to a second data synthetization machine learning model, second data received from a second data source group. The computing device determines an allocation of resources based at least in part on comparing the first data and the first synthetic data with the second data and the second synthetic data.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: In some examples, a computing device may receive data from a plurality of groups of data sources. The computing device may access a plurality of data synthetization machine learning models configured for generating synthetic data. Respective ones of the data synthetization machine learning models may correspond to respective ones of the groups of data sources. The computing device generates first synthetic data by inputting, to a first data synthetization machine learning model, first data received from a first data source group, and generates second synthetic data by inputting, to a second data synthetization machine learning model, second data received from a second data source group. The computing device determines an allocation of resources based at least in part on comparing the first data and the first synthetic data with the second data and the second synthetic data.

Abstract: A behavior detection module receives a training database and applies a transformation to the attributes that improves the uniformity of the values associated with each attribute. The transformed training database is used to construct a random forest classifier (RFC). The RFC includes a plurality of decision trees and generates a classification label estimate for a data entry with a plurality of attributes. The classification label estimate is determined based on classification estimates from the plurality of decision trees. Each parent node of a decision tree is associated with a condition of a transformed attribute that directs the data entry to a corresponding child node depending on whether the condition is satisfied or not. The data entry is directed through the tree to one out of a set of leaf nodes, and a classification label associated with the leaf node.

Abstract: In some examples, a computing device may receive data from a plurality of groups of data sources. The computing device may create a training data set from a first portion of the received data and may create a plurality of validation data sets from a second portion of the received data. For example, each validation data set may correspond to a respective one of the groups of data sources. The computing device may train, using the training data set, a plurality of machine learning models configured for synthesizing data. For instance, respective ones of the machine learning models may correspond to respective ones of the groups of data sources. Further, the computing device may validate the respective machine learning models using the respective validation data set corresponding to the respective group to which the respective machine learning model being validated corresponds.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: A method and system for generating automated front-end code for a website from design files is described. In one embodiment, a method for generating automated front-end code for a website includes obtaining at least one design file associated with a design of a website from a client device. Hypertext markup language (HTML) code and a cascading style sheet (CSS) file is automatically generated from the at least one design file from information obtained from a plurality of layers associated with the design file. The method includes extracting a plurality of extracted image files from the at least one design file. The method further includes providing front-end code for the website that includes the HTML code, the CSS file, and the plurality of extracted image files to the client device.

Abstract: A system for bidder support in combinatorial auctions includes a machine readable storage medium storing instructions and a processor to execute the instructions throughout a duration of an auction. The processor executes the instructions to receive bids for a multi-item multi-unit (MIMU) combinatorial auction. The processor executes the instructions to track the status of each sub-auction of the MIMU auction. The status for each sub-auction includes a value of the respective sub-auction and a last winning bid of the respective sub-auction. The processor executes the instructions to determine bidder support information including winning levels, deadness levels, winning bids, and live bids based on the status of each sub-auction.

Abstract: System and method for performing experiments. For example, the method includes receiving indications of experimental workflows, generating workflow configuration requirements for each experimental workflow, configuring each experimental workflow based upon parameters associated with the workflow configuration requirements, receiving experimental requests for the experimental workflows, determining a schedule for executing the experimental requests, assigning each experimental request one or more remote laboratories for execution based upon the schedule, generating a set of instructions for performing experiments related to each experimental request, determining a plurality of sequence schedules for completing the set of instructions, receiving an indication of a sequence schedule selected from the plurality of sequence schedules, and transmitting commands to execute the set of instructions according to the selected sequence schedule.

Abstract: System and method for managing one or more experimental requests. For example, the method includes receiving multiple experimental requests, determining a schedule for executing the multiple experimental requests based upon attributes associated with each experimental request, and assigning the multiple experimental requests to remote laboratories for execution based upon the schedule and features of the remote laboratories.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: A packet forwarding network may include spine and leaf switches that forward network traffic between end hosts. The packet forwarding network may be implemented on multiple network racks in a rack-based system. A controller may control the underlying spine and leaf switches to form on-premise virtual private cloud (VPC) resources. In particular, the controller may form enterprise VPC (EVPC) tenants, each having a virtual router that performs routing between different segments within the corresponding EVPC tenant. The different segments may separately include web, application, and database servers, as end hosts. The controller may form a system VPC tenant having a virtual system router that performs routing between different EVPC tenants. A segment in an internal VPC tenant formed by the controller and/or an external VPC tenant formed by the controller may provide external network access for one or more of the EVPC tenants.

Abstract: In some examples, a computing device may receive data from a plurality of groups of data sources. The computing device may create a training data set from a first portion of the received data and may create a plurality of validation data sets from a second portion of the received data. For example, each validation data set may correspond to a respective one of the groups of data sources. The computing device may train, using the training data set, a plurality of machine learning models configured for synthesizing data. For instance, respective ones of the machine learning models may correspond to respective ones of the groups of data sources. Further, the computing device may validate the respective machine learning models using the respective validation data set corresponding to the respective group to which the respective machine learning model being validated corresponds.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: A data system includes a plurality of storage drives each comprising a multi-lane serial drive interface. The data system also includes a control system configured to receive, over a host link, a write operation for storage of data, process a storage address of the write operation against storage allocation information to apportion the data for storage among more than one target storage drive, and transfer corresponding portions of the data to the target storage drives.

Abstract: The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a memory device comprises a memory interface, an ECC generation component, and storage components. The memory interface is configured to receive an access request to an address at which data is stored. The memory interface can also forward responses to the request including the data and ECC information associated with the data. The ECC generation component is configured to automatically establish an address at which the ECC information is stored based upon the receipt of the access request to an address at which data is stored. In one exemplary implementation, the internal establishment of the address at which the ECC information is stored is automatic. The storage components are configured to store the information.