Abstract: In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Abstract: A 4.times.1 multiplexer for an electrically configurable device uses novel logic gates to logically combine outputs from two SRAM memory cells to control pass gates between the multiplexer signal inputs and a multiplexer output. Each logic gate has three transistors. A complementary NMOS/PMOS pair of transistors defines a transmission gate. The gate of the NMOS transistor defines a first logic-gate input, while the gate of the PMOS transistor defines a second logic-gate input. Their sources are coupled and cooperatively define a third logic-gate input. Their drains are coupled and cooperatively define the logic-gate output. A third transistor, with its gate tied to the third input, couples the logic-gate output to ground when the transmission gate is OFF. The first and second logic-gate inputs are respectively coupled to complementary outputs of one memory cell, while the third logic gate input is coupled to an output of the other memory cell.

Abstract: In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Abstract: A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can also be programmably interconnected so that two signal channels are formed. The present invention modifies the known six transistor switch box so that one line output from the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors switch box is significantly reduced. For short line lengths, the buffer delay can be greater than the delay associated with the resistance and capacitance of the transistors of the switch box. In these cases, the output is not buffered and the buffer is programmably bypassed.