Abstract: Apparatus, systems, and techniques to share memory. In at least one embodiment, a processor comprises one or more circuits to allocate memory to at least two heterogeneous processing cores in response to performing one or more instructions associated with one or more application programming interfaces based, at least in part, on one or more attributes associated with the at least two heterogeneous processing cores.

Abstract: An embodiment of a system is disclosed, including an interface configured to communicate to a device under test (DUT). The DUT may include a plurality of processor cores. The system also includes a testing apparatus configured to concurrently measure a performance of a portion of each processor core to generate a first set of test values. Each test value of the first set may correspond to a given processor core of the plurality of processor cores. The testing apparatus may also be configured to analyze the first set of test values, and reject the DUT in response to a determination that at least one test value of the first set of test values exceeds a first threshold.

Abstract: An embodiment of a system is disclosed, including an interface configured to communicate to a device under test (DUT). The DUT may include a plurality of processor cores. The system also includes a testing apparatus configured to concurrently measure a performance of a portion of each processor core to generate a first set of test values. Each test value of the first set may correspond to a given processor core of the plurality of processor cores. The testing apparatus may also be configured to analyze the first set of test values, and reject the DUT in response to a determination that at least one test value of the first set of test values exceeds a first threshold.

Abstract: Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for allocating, dividing and accessing memory of a multi-threaded computing system based at least in part on the structural hierarchy of the components of the computing system. Allocating partitions of memory based on the hierarchy structure of the computing system may isolate the threads of the computing system such that cache-memory contention by a plurality of executing threads may be reduced. In general, the apparatus and/or method may analyze the hierarchal structure of the components of the computing system utilized in the execution of applications and divide the available memory of the system between the various components. This division of the system memory creates exclusive partitions in the caches of the computing system based on the processor and cache hierarchy. The partitions may be used by different applications or by different sections of the same application to store accessed memory in cache for quick retrieval.

Abstract: Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.