Patents by Inventor Alok Prakash Joshi

Alok Prakash Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11625056
    Abstract: According to an aspect a low noise electronic voltage regulator comprises a regulating transistor operative to regulate an input DC voltage to provide a regulated DC output voltage, an error amplifier configured to generate an error signal based on a reference voltage and a feedback voltage, wherein the error amplifier receiving the feedback voltage through a feedback loop formed between the regulated DC output voltage and the feedback voltage, and a first amplifier in the feedback loop providing a gain of greater than unity from the regulated DC output voltage and the feedback voltage.
    Type: Grant
    Filed: July 31, 2021
    Date of Patent: April 11, 2023
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20220291705
    Abstract: According to an aspect a low noise electronic voltage regulator comprises a regulating transistor operative to regulate an input DC voltage to provide a regulated DC output voltage, an error amplifier configured to generate an error signal based on a reference voltage and a feedback voltage, wherein the error amplifier receiving the feedback voltage through a feedback loop formed between the regulated DC output voltage and the feedback voltage, and a first amplifier in the feedback loop providing a gain of greater than unity from the regulated DC output voltage and the feedback voltage.
    Type: Application
    Filed: July 31, 2021
    Publication date: September 15, 2022
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 10784215
    Abstract: According to an aspect of the present invention, an electronic system (499) operative on a millimeter signal comprises an integrated circuit (401) comprising a first solder ball (420A) and a second solder ball (420B) respectively coupled to a positive and a negative signal interface points (412 and 413) of a differential millimeter signal on a die (410) housed in the integrated circuit (401), wherein the first and the second solder balls (420A and 420B) are positioned one behind other from an edge of the integrated circuit (401) and a three-path coplanar waveguide (CPW) comprising a center path (495B) and a two adjacent paths (495A and 495C) formed on a printed circuit board (PCB) (490) such that the center path (495B) is coupled to the first solder ball that is in front and the two adjacent paths coupled to the second solder ball that is behind the first solder ball.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 22, 2020
    Inventors: Apu Sivadas, Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 10734966
    Abstract: According to an aspect of present disclosure, a phase shifter for providing a desired phase shift to a very high frequency signal fabricated as part of the an integrated circuit comprises a first coil segment and a second coil segment together forming an inductor of first inductance value, a first capacitor of first capacitance value electrically connected parallel the inductor, a second capacitor of second capacitance value electrically connected between the first coil segment and the second coil segment and a resistor of a first resistance value electrically connected parallel to the second capacitor, in that, the inductor, first capacitor, second capacitor and the resistor together operative as a phase shifter such that when a input signal of a first frequency is presented across the first capacitor, the output signal across the resistor is phase shifted version of the input signal shifted in phase by a first angle.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 4, 2020
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Rakesh Kumar
  • Publication number: 20200161257
    Abstract: According to an aspect of the present invention, an electronic system (499) operative on a millimeter signal comprises an integrated circuit (401) comprising a first solder ball (420A) and a second solder ball (420B) respectively coupled to a positive and a negative signal interface points (412 and 413) of a differential millimeter signal on a die (410) housed in the integrated circuit (401), wherein the first and the second solder balls (420A and 420B) are positioned one behind other from an edge of the integrated circuit (401) and a three-path coplanar waveguide (CPW) comprising a center path (495B) and a two adjacent paths (495A and 495C) formed on a printed circuit board (PCB) (490) such that the center path (495B) is coupled to the first solder ball that is in front and the two adjacent paths coupled to the second solder ball that is behind the first solder ball.
    Type: Application
    Filed: February 4, 2019
    Publication date: May 21, 2020
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Apu Sivadas, Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 10382036
    Abstract: Disclosed is circuitry for operating a switch which sees high voltage swings across its source, gate, drain, and bulk terminals. The circuitry generates one or more bias voltages in proportion to an input voltage swing. The one or more bias voltages may be used to bias the gate and bulk terminals to provide reliable and improved turn OFF performance in the switch.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 13, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20190229699
    Abstract: According to an aspect of present disclosure, a phase shifter for providing a desired phase shift to a very high frequency signal fabricated as part of the an integrated circuit comprises a first coil segment and a second coil segment together forming an inductor of first inductance value, a first capacitor of first capacitance value electrically connected parallel the inductor, a second capacitor of second capacitance value electrically connected between the first coil segment and the second coil segment and a resistor of a first resistance value electrically connected parallel to the second capacitor, in that, the inductor, first capacitor, second capacitor and the resistor together operative as a phase shifter such that when a input signal of a first frequency is presented across the first capacitor, the output signal across the resistor is phase shifted version of the input signal shifted in phase by a first angle.
    Type: Application
    Filed: March 26, 2018
    Publication date: July 25, 2019
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Rakesh Kumar
  • Patent number: 9893702
    Abstract: A notch filter including an inductor-capacitor tuning circuit is disclosed. The inductor-capacitor tuning circuit may determine a frequency response of the notch filter in accordance with an associated resonant frequency. In some exemplary embodiments, the inductor-capacitor circuit may include a differential inductor divided at a symmetry point and a variable capacitor coupled to the differential inductor at the symmetry point.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Apu Sivadas
  • Patent number: 9692375
    Abstract: Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9608569
    Abstract: A method and apparatus for linearizing a baseband filter are provided. The apparatus is configured to, via a first conducting module, receive a first current signal. The apparatus is further configured to, via a converting module, receive a second current signal, generate a voltage signal based on the second current signal, and apply the voltage signal to the first conducting module. An amount of the second current signal received by the converting module is based on an amount of the first current signal flowing through the first conducting module. The apparatus is also configured to, via a second conducting module, control an output current signal based on the voltage signal. The output current signal is controlled to be a linear replica of the first current signal for in-band frequencies.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: March 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Bhushan Shanti Asuri, Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9595919
    Abstract: Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 14, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Ashish Lachhwani
  • Publication number: 20170033750
    Abstract: Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.
    Type: Application
    Filed: September 17, 2015
    Publication date: February 2, 2017
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20170033757
    Abstract: A notch filter including an inductor-capacitor tuning circuit is disclosed. The inductor-capacitor tuning circuit may determine a frequency response of the notch filter in accordance with an associated resonant frequency. In some exemplary embodiments, the inductor-capacitor circuit may include a differential inductor divided at a symmetry point and a variable capacitor coupled to the differential inductor at the symmetry point.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 2, 2017
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Apu Sivadas
  • Publication number: 20160380592
    Abstract: Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Ashish Lachhwani
  • Publication number: 20160294327
    Abstract: A method and apparatus for linearizing a baseband filter are provided. The apparatus is configured to, via a first conducting module, receive a first current signal. The apparatus is further configured to, via a converting module, receive a second current signal, generate a voltage signal based on the second current signal, and apply the voltage signal to the first conducting module. An amount of the second current signal received by the converting module is based on an amount of the first current signal flowing through the first conducting module. The apparatus is also configured to, via a second conducting module, control an output current signal based on the voltage signal. The output current signal is controlled to be a linear replica of the first current signal for in-band frequencies.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 6, 2016
    Inventors: Bhushan Shanti ASURI, Alok Prakash JOSHI, Gireesh RAJENDRAN
  • Publication number: 20160226488
    Abstract: Disclosed is circuitry for operating a switch which sees high voltage swings across its source, gate, drain, and bulk terminals. The circuitry generates one or more bias voltages in proportion to an input voltage swing. The one or more bias voltages may be used to bias the gate and bulk terminals to provide reliable and improved turn OFF performance in the switch.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9083075
    Abstract: A device includes multiple transceivers, a coupling block and an antenna. The transceivers operate according to time-division multiple access (TDMA) techniques. The coupling block is designed to enable the multiple transceivers to transmit or receive corresponding signals using the antenna. The multiple transceivers include a first transmitter and a second transmitter. The first transmitter is connected to the antenna via a first coupling network. The second transmitter is connected to the antenna via a series connection of a second coupling network and at least a portion of the first coupling network. Other transmitters are connected to the antenna via a series arrangement of at least a portion of the first coupling network and corresponding coupling networks.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 14, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Apu Sivadas
  • Patent number: 8975961
    Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20140347124
    Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20140312474
    Abstract: A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire bonding site and a second substrate wire bonding site. A first bondwire is connected between the first die wire bonding site and the first substrate wire bonding site and a second bondwire is connected between the second die wire bonding site and the second substrate wire bonding site. The first and second bondwires lie in adjacent, substantially parallel bondwire planes. The second bondwire is substantially skewed with respect to said first bondwire.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Brian Parks