Abstract: Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

Abstract: Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

Abstract: A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.