Abstract: Embodiments include a system on chip (SOC) comprising: a cache; a buffer manager configured to manage a plurality of buffer locations; and a processing core configured to issue a buffer allocation request to the buffer manager to request the buffer manager to allocate one or more buffer locations to the processing core, the buffer manager being further configured to, in response to receiving the buffer allocation request, allocate a first buffer location to the processing core by writing a first buffer pointer associated with the first buffer location to the cache, and the processing core being further configured to obtain the allocation of the first buffer location by reading the first buffer pointer from the cache.

Abstract: Embodiments include a system on chip (SOC) comprising: a cache; a buffer manager configured to manage a plurality of buffer locations; and a processing core configured to issue a buffer allocation request to the buffer manager to request the buffer manager to allocate one or more buffer locations to the processing core, the buffer manager being further configured to, in response to receiving the buffer allocation request, allocate a first buffer location to the processing core by writing a first buffer pointer associated with the first buffer location to the cache, and the processing core being further configured to obtain the allocation of the first buffer location by reading the first buffer pointer from the cache.

Abstract: A blanking interval information decoder is described, with the blanking interval decoder being adapted for decoding blanking interval information transmitted in a video signal. The blanking interval information decoder comprises a processing unit, a memory adapted for storing at least one of code and data, and a set of blanking interval decoding routines stored in the memory. Each of the blanking interval decoding routines is adapted for decoding a certain type of blanking interval information of a certain video standard.