Patents by Inventor Alon Shoshani

Alon Shoshani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device and method for scheduling transactions over a deep pipelined component
    Patent number: 8341322
    Abstract: A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: December 25, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dror Gilad, Ori Goren, Alon Shoshani
  • DEVICE AND METHOD FOR SCHEDULING TRANSACTIONS OVER A DEEP PIPELINED COMPONENT
    Publication number: 20100030940
    Abstract: A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.
    Type: Application
    Filed: March 7, 2007
    Publication date: February 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Dror Gilad, Ori Goren, Alon Shoshani