Abstract: In one embodiment, a system for handling out-of-order memory responses in a multi-processor environment includes a plurality of processors, a shared reorder buffer coupled to the plurality of processors, and a plurality of transaction identification (ID) assignment logic units, each associated with a respective processor of the plurality of processors, wherein each transaction ID assignment logic unit is to assign transaction IDs to memory requests issued by the respective processor, and the shared reorder buffer is to store and reorder memory responses to the memory requests based on the assigned transaction IDs.

Abstract: Methods and devices for isolating microbial cells from a sample, extracting eukaryotic DNA from a sample, and identifying the microbial species in the sample are disclosed herein.

Abstract: Fluidic devices and related methods are generally provided. The fluidic devices described herein may be useful, for example, for diagnostic purposes (e.g., detection of the presence of one or more disease causing bacteria in a patient sample). Unlike certain existing fluidic devices for diagnostic purposes, the fluidic devices and methods described herein may be useful for detecting the presence of numerous disease causing bacteria in a patient sample substantially simultaneously (e.g., in parallel). In some embodiments, the fluidic devices and methods described herein provide highly sensitive detection of microbes in relatively large fluidic samples (e.g., between 0.5 mL and about 5 mL), as compared to certain existing fluidic detection (e.g., microfluidic) devices and methods. In an exemplary embodiment, increased detection sensitivity of microbial pathogens present in a patient sample (e.g., blood) is performed by selectively removing human nucleic acid prior to sensitive detection of microbial infection.

Abstract: A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

Abstract: The present disclosure generally relates to the field of microbial pathogen detection and identification utilizing genomic sequence recognition.

Abstract: A computer system includes a processor and a Duplicate Write Circuit (DWC). The DWC is to hold a definition that specifies an address range and a plurality of additional address ranges, and to receive, from the processor, a write command that specifies a write-data and a write-address. When the write-address falls outside the address range, the DWC is to generate a write cycle that writes the write-data to the address. When the write-address falls in the address range, the DWC is to generate (i) the write cycle that writes the write-data to the address, and (ii) a sequence of additional write cycles that write the write-data to corresponding addresses in the additional address ranges.

Abstract: A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

Abstract: A computer system includes a processor and a Duplicate Write Circuit (DWC). The DWC is to hold a definition that specifies an address range and a plurality of additional address ranges, and to receive, from the processor, a write command that specifies a write-data and a write-address. When the write-address falls outside the address range, the DWC is to generate a write cycle that writes the write-data to the address. When the write-address falls in the address range, the DWC is to generate (i) the write cycle that writes the write-data to the address, and (ii) a sequence of additional write cycles that write the write-data to corresponding addresses in the additional address ranges.

Abstract: In one embodiment, a system includes a network device application-specific integrated circuit (ASIC), which includes a microcontroller to provide a command to a hardware accelerator to perform a job including gathering telemetry data from at least one hardware unit and write the gathered telemetry data to a memory, and the hardware accelerator to gather the telemetry data from the at least one hardware unit and write the gathered telemetry data to the memory based on the command.

Abstract: A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

Abstract: Fluidic devices and related methods are generally provided. The fluidic devices described herein may be useful, for example, for diagnostic purposes (e.g., detection of the presence of one or more disease causing bacteria in a patient sample). Unlike certain existing fluidic devices for diagnostic purposes, the fluidic devices and methods described herein may be useful for detecting the presence of numerous disease causing bacteria in a patient sample substantially simultaneously (e.g., in parallel). In some embodiments, the fluidic devices and methods described herein provide highly sensitive detection of microbes in relatively large fluidic samples (e.g., between 0.5 mL and about 5 mL), as compared to certain existing fluidic detection (e.g., microfluidic) devices and methods. In an exemplary embodiment, increased detection sensitivity of microbial pathogens present in a patient sample (e.g., blood) is performed by selectively removing human nucleic acid prior to sensitive detection of microbial infection.

Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

Abstract: Fluidic devices and related methods are generally provided. The fluidic devices described herein may be useful, for example, for diagnostic purposes (e.g., detection of the presence of one or more disease causing bacteria in a patient sample). Unlike certain existing fluidic devices for diagnostic purposes, the fluidic devices and methods described herein may be useful for detecting the presence of numerous disease causing bacteria in a patient sample substantially simultaneously (e.g., in parallel). In some embodiments, the fluidic devices and methods described herein provide highly sensitive detection of microbes in relatively large fluidic samples (e.g., between 0.5 mL and about 5 mL), as compared to certain existing fluidic detection (e.g., microfluidic) devices and methods. In an exemplary embodiment, increased detection sensitivity of microbial pathogens present in a patient sample (e.g., blood) is performed by selectively removing human nucleic acid prior to sensitive detection of microbial infection.

Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

Abstract: An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.

Abstract: The present disclosure generally relates to the field of microbial pathogen detection and identification utilizing genomic sequence recognition.

Abstract: The present disclosure generally relates to the field of ultrasensitive microbial pathogen detection and identification utilizing genomic sequence recognition.

Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

Abstract: The present disclosure generally relates to the field of microbial pathogen detection and identification utilizing genomic sequence recognition.

Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.