Abstract: An integrated electronic memory circuit is provided which includes memory circuitry for storing binary data in an array of memory locations; first data signal providing circuitry for providing input data signals to the memory circuitry, for storage by the memory circuitry as binary data at respective memory locations; and write signal generator circuitry for generating a write signal causing the memory circuitry to accept input data signals from the first data signal providing circuitry for storing in the array.

Abstract: An apparatus for storing data for read and write access receiving reset control signals, comprising a plurality of storage blocks, each block including an array of memory units for storing a unit of data is provided that is reset along storage block boundaries. A reset control means, coupled to receive the reset control signals which identify at least one of the storage blocks, is included for generating block reset signals. A means, coupled to the memory units in each storage block and to receive the block reset signals, for resetting the identified block of memory to 0. .

Abstract: A tag buffer having built-in testing capabilities is disclosed. In a single-chip, integrated-circuit design which includes a SRAM, a parity generator and checker, and a comparator, a method and capability of testing the functionality of the SRAM and parity components is defined. For an embodiment in which the SRAM component includes a redundancy scheme for replacing a defective memory array row, a test for determining whether a redundant row has been used is also provided.

Abstract: A memory comprising a plurality of memory cells, a column decoder, a row decoder, a plurality of shift registers and a multiplexer is provided for addressing the memory cells in a conventional manner or in a high-speed sequential mode. In the sequential mode alternate cells from each of two sets of cells are addressed and their contents provided on a data output line, or data presented to them on a data input line, at a system clock rate which is much faster than the conventional mode.