Abstract: An improved buffer circuit, particularly a pulse controlled impedance compensated output buffer. The improvement includes two drivers which are activated during a portion of the switching time of the output. The two drivers are activated for different durations which partially encompass the output transition and may be overlapping. A feedback circuit may also be used, providing further impedance compensation. By the feedback circuit actuating a driver in response to a difference between a reference signal level and an output signal level, the total output drive strength of the buffer is better tailored to the load impedance. The reference signal level may be sampled at a point during the output transition.