Abstract: According to an embodiment of present invention, an algorithm for computing static pre-equalizer coefficients, comprises the steps of determining a length of algorithm iterations; calculating a feedforward coefficient vector associated with a feedforward equalizer; calculating a pre-equalizer coefficient vector associated with a pre-equalizer filter; and performing the steps of calculating for the length of the algorithm iterations; wherein a mean square of an error between an output sequence and a transmitted digital input sequence is minimized.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: According to an embodiment of present invention, an algorithm for computing static pre-equalizer coefficients, comprises the steps of determining a length of algorithm iterations; calculating a feedforward coefficient vector associated with a feedforward equalizer; calculating a pre-equalizer coefficient vector associated with a pre-equalizer filter; and performing the steps of calculating for the length of the algorithm iterations; wherein a mean square of an error between an output sequence and a transmitted digital input sequence is minimized.

Abstract: An embodiment of the present invention is directed to a rate enhanced system for supporting duplex transmission of symmetric data rates. The system comprises an encoder comprising a serial to parallel converter for receiving a serial data bit, and for generating a parallel word having M bits; a convolutional encoder for receiving a first bit of the M bits of the parallel word, and for generating two encoded bits; and a mapper for receiving the two encoded bits and the remaining M−1 bits of the parallel word, and for generating a symbol; wherein M is greater than three.

Abstract: A minimum mean square error linearly constrained fast algorithm for adaptive training of a Time Domain Equalizer (MLC-TEQ) is provided. A fast adaptive algorithm of the present invention may be used to obtain Finite Impulse Response (FIR) filter coefficients for Time domain Equalizer (TEQ) used in Discrete Multitone (DMT) based applications, such as ADSL, for example. The TEQ coefficients obtained by the algorithm of the present invention shortens the overall effective discrete time channel impulse response length within a given target length (e.g., symbol prefix length for DMT application). Advantages of the proposed data aided adaptive algorithm may include providing the TEQ filter coefficients with near-optimal performance; having low computational requirements, having fast convergence, and exhibiting attractive stability properties. Other advantages may also be realized by the present invention and variations thereof.

Abstract: A dual rate echo canceller is provided for applications with asymmetric transmit and receive rates. In particular, the present invention provides Reduced Complexity Dual Rate Echo Canceller (RCDR-EC) architecture along with low complexity Least Mean Square (LMS) update rules. According to one aspect, the present invention is directed to an echo canceller that provides rate matching functionality for applications (e.g., ADSL, VDSL, etc.) with asymmetric data rates. The RCDR-EC of the present invention operates at the lower of the two rates, receive and transmit, requiring less computation per data sample. RCDR-EC implements a significantly smaller length echo cancellation filter (ECF) for achieving the same (or similar) level of echo suppression of conventional implementations. This reduces the hardware requirement for implementation of RCDR-EC.

Abstract: A TEQ filter is provided for applications with asymmetric transmit and receive rates, such as for use in, for example, ADSL and VDSL applications. In particular, the present invention provides for a physical layer solution in which a channel impulse response is shortened by modeling a desired target impulse response based on a hypothetical delay channel. The target channel length is approximately matched to yield a set of TEQ filter coefficients or family of parameters. The TEQ filter coefficients or parameters when applied to the given channel impulse response yields a shortened channel impulse response to improve efficiency of data flow. Channel effects, receiver effects and other noise or disturbance effects are considered in modeling the system to derive the TEQ filter coefficients to generate the desired shortened channel impulse response.

Abstract: A weighted error echo canceller for transceivers with unequal bandwidths is provided. The present invention enables an adaptive echo cancellation filter to perform at a lower sample rate. An efficient echo cancellation scheme, referred to as Weighted Vector Error Echo Canceller (WEVE-EC) is proposed for various applications, such as applications where the receive path has a higher sampling rate. The WEVE-EC architecture may be implemented along with an adaptive algorithm, which may be based on Least Mean Square (LMS) update rules. Various other adaptive algorithms may be used to train the WEVE-EC of the present invention. An Error Weighting Multi-input-multi-output Filter (EWMF) of the present invention provides a flexible weighting scheme on most or all the sampling phases of the error signal.