Patents by Inventor Alpesh B. Oza

Alpesh B. Oza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for the definition and generation of configurable, high performance low-power embedded microprocessor cores
    Patent number: 9329872
    Abstract: A system and method for configuring a microprocessor core may allow a microprocessor core to be configurable. Configuration may be dynamic or automatic using an application program. Microprocessor memory, decoding units, arithmetic logic units, register banks, storage, register bypass units, and a user interface may be configured. The configuration may also be used to optimize an instruction set to run on the microprocessor core.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: May 3, 2016
    Assignee: ESENCIA TECHNOLOGIES INC.
    Inventors: Miguel A. Guerrero, Alpesh B. Oza
  • Method and Apparatus for the Automatic Generation of RTL from an Untimed C or C++ Description as a Fine-Grained Specialization of a Micro-processor Soft Core
    Publication number: 20130290693
    Abstract: A system and method for configuring a configuring a register transfer level description from a programming language may utilize a configurable microprocessor core. A compiler may compile the programming language using performance statistics and user constraints. A template processor may translate the programming language into register transfer level description language using template files. Timing and area constraints may be used prior to output a gate level netlist ready to place on a microchip.
    Type: Application
    Filed: May 10, 2013
    Publication date: October 31, 2013
    Applicant: ESENCIA TECHNOLOGIES INC.
    Inventors: Miguel A. Guerrero, Alpesh B. Oza
  • Method and Apparatus for the Definition and Generation of Configurable, High Performance Low-Power Embedded Microprocessor Cores
    Publication number: 20130290692
    Abstract: A system and method for configuring a microprocessor core may allow a microprocessor core to be configurable. Configuration may be dynamic or automatic using an application program. Microprocessor memory, decoding units, arithmetic logic units, register banks, storage, register bypass units, and a user interface may be configured. The configuration may also be used to optimize an instruction set to run on the microprocessor core.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 31, 2013
    Applicant: Esencia Technologies Inc.
    Inventors: MIguel A. GUERRERO, Alpesh B. OZA
  • Memory controller module having independent memory controllers for different memory types
    Patent number: 7308526
    Abstract: A memory controller module that includes a memory interface and at least two memory controllers, each memory controller to control a category of memory devices. A circuitry enables the at least two memory controllers to control access to memory devices based on information indicating the category or categories of the memory devices coupled to the memory interface.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Alpesh B. Oza, Rohit R. Verma
  • Error correction for memory
    Patent number: 7203889
    Abstract: A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity information, read the error correction information if there is error as determined based on the parity information.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Alpesh B. Oza, Miguel A. Guerrero, Rohit R. Verma
  • Method and apparatus for high-speed address learning in sorted address tables
    Publication number: 20030163445
    Abstract: Described herein is a method and apparatus for high-speed address learning in sorted address tables.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Inventors: Alpesh B. Oza, Miguel A. Guerrero