Abstract: In an integrated circuit of the type having a reset transistor for a capacitance succeeded by an active information charge transfer transistor for the capacitance, a clock pulse signal at the common switching electrode results in opposite-polarity switching. It is found in practice that a noise pattern present at a reset pulse level in the circuit output signal may cause problems in the case of further signal processing operations in the device. To solve these problems, a control method is used with a clock pulse signal which has three signal levels, a first level at which only the reset transistor is conducting, a second level at which the two transistors are both non-conducting, and a third level at which only the information charge transfer transistor is conducting.