Patents by Inventor Altug Koker

Altug Koker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FABRIC-BASED COMPRESSION/DECOMPRESSION FOR INTERNAL DATA TRANSFER
    Publication number: 20210125379
    Abstract: A mechanism is described for facilitating fabric-based compression and/or decompression of data at computing devices. A method of embodiments, as described herein, includes compressing contents of a data stream traveling through an internal fabric between a source component and a destination component, wherein the contents are compressed on the internal fabric.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Altug Koker, Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu
  • SMART COMPRESSION/DECOMPRESSION SCHEMES FOR EFFICIENCY AND SUPERIOR RESULTS
    Publication number: 20210125378
    Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.
    Type: Application
    Filed: September 3, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: ABHISHEK R. APPU, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
  • INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING
    Publication number: 20210124579
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Application
    Filed: December 9, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE
    Publication number: 20210125581
    Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, James A. Valerio, Prasoonkumar Surti, Abhishek R. Appu, Vasanth Ranganathan, Kalyan K. Bhiravabhatla, Arthur D. Hunter, JR., Wei-Yu Chen, Subramaniam M. Maiyuran
  • Control flow mechanism for execution of graphics processor instructions using active channel packing
    Patent number: 10990409
    Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 27, 2021
    Assignee: INTEL CORPORATION
    Inventors: Subramaniam M. Maiyuran, Guei-Yuan Lueh, Supratim Pal, Gang Chen, Ananda V. Kommaraju, Joy Chandra, Altug Koker, Prasoonkumar Surti, David Puffer, Hong Bin Liao, Joydeep Ray, Abhishek R. Appu, Ankur N. Shah, Travis T. Schluessler, Jonathan Kennedy, Devan Burke
  • Resource load balancing based on usage and power limits
    Patent number: 10983581
    Abstract: Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Altug Koker, Yoav Harel, Kenneth Brand, Chandra Gurram, Eric Finley, Bhushan Borole, Carlos Nava Rodriguez
  • Memory compression hashing mechanism
    Patent number: 10983906
    Abstract: An apparatus to facilitate memory data compression is disclosed. The apparatus includes a memory and having a plurality of banks to store main data and metadata associated with the main data and a memory management unit (MMU) coupled to the plurality of banks to perform a hash function to compute indices into virtual address locations in memory for the main data and the metadata and adjust the metadata virtual address locations to store each adjusted metadata virtual address location in a bank storing the associated main data.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Niranjan Cooray, Prasoonkumar Surti, Sudhakar Kamma, Vasanth Ranganathan
  • Sensory enhanced augmented reality and virtual reality device
    Patent number: 10983594
    Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, James M. Holland, Pattabhiraman K, Sayan Lahiri, Radhakrishnan Venkataraman, Kamal Sinha, Ankur N. Shah, Deepak S. Vembar, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall
  • Handling pipeline submissions across many compute units
    Patent number: 10977762
    Abstract: One embodiment provides for a general-purpose graphics processing unit multiple processing elements having a single instruction, multiple thread (SIMT) architecture configured to perform hardware multithreading during execution of a plurality of thread groups. The plurality of thread groups can include one or more sub-groups of threads, with a first sub-group is associated with a first thread group and a second sub-group associated with a second thread group. Data dependencies can be used to trigger the launch of threads, such that when a first thread in the second sub-group has a data dependency upon a first thread in the first sub-group, circuitry in the general-purpose graphics processing unit can launch at least the first thread in the second sub-group to execute in response to satisfaction of the data dependency.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Altug Koker, Joydeep Ray
  • Augmented reality and virtual reality feedback enhancement system, apparatus and method
    Patent number: 10964091
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Chandrasekaran Sakthivel, Michael Apodaca, Kai Xiao, Altug Koker, Jeffery S. Boles, Adam T. Lake, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, James M. Holland, Prasoonkumar Surti, Jonathan Kennedy, Louis Feng, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Adaptive compute size per workload
    Patent number: 10963986
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 30, 2021
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Josh B. Mastronarde, Altug Koker, Nikos Kaburlasos, Abhishek R. Appu, Joydeep Ray
  • Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices
    Patent number: 10957008
    Abstract: A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Kiran C. Veernapu, Mohammed Tameem, Altug Koker, Abhishek R. Appu
  • Power consumption management for communication bus
    Patent number: 10955896
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Eric J. Hoekstra, Kiran C. Veernapu, Prasoonkumar Surti, Vasanth Ranganathan, Kamal Sinha, Balaji Vembu, Eric J. Asperheim, Sanjeev S. Jahagirdar, Joydeep Ray
  • Extend GPU/CPU coherency to multi-GPU cores
    Patent number: 10956330
    Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Chandrasekaran Sakthivel, Prasoonkumar Surti, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Abhishek R. Appu, Nicolas C. Galoppo Von Borries, Joydeep Ray, Narayan Srinivasa, Feng Chen, Ben J. Ashbaugh, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Eriko Nurvitadhi, Balaji Vembu, Altug Koker
  • High bandwidth connection between processor dies
    Patent number: 10956223
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu
  • Coarse grain coherency
    Patent number: 10949945
    Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, James A. Valerio, David Puffer, Abhishek R. Appu, Stephen Junkins
  • Transitionary pre-emption for virtual reality related contexts
    Patent number: 10942740
    Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, Abhishek R. Appu
  • EFFICIENT MERGING OF ATOMIC OPERATIONS AT COMPUTING DEVICES
    Publication number: 20210065329
    Abstract: A mechanism is described for facilitating dynamic merging of atomic operations in computing devices. A method of embodiments, as described herein, includes facilitating detecting atomic messages and a plurality of slot addresses. The method further includes comparing one or more slot addresses of the plurality of slot addresses with other slot addresses of the plurality of slot addresses to seek one or more matched slot addresses, where the one or more matched slot addresses are merged into one or more merged groups. The method may further include generating one or more merged atomic operations based on and corresponding to the one or more merged groups.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 4, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Abhishek R. Appu, Balaji Vembu
  • System, Apparatus And Method For Segmenting A Memory Array
    Publication number: 20210065779
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 4, 2021
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhishek R. Appu
  • Apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor
    Patent number: 10937123
    Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Pattabhiraman K, Matthew B. Callaway