Abstract: This document discusses, among other things, apparatus and methods to optimize charging of a battery, including providing a first charge profile configured to provide charge current pulses to a battery in a plurality of steps. In the first charge profile, the charge current pulses can be stepped down in the plurality of steps using a comparison of a terminal voltage of the battery to a clamp voltage. When the terminal voltage meets or exceeds the clamp voltage, a high time current of the charge current pulse can be decreased and the clamp voltage can be increased before providing a subsequent charge current pulse.

Abstract: This document discusses, among other things, apparatus and methods to optimize charging of a battery, including providing a first charge profile configured to provide charge current pulses to a battery in a plurality of steps. In the first charge profile, the charge current pulses can be stepped down in the plurality of steps using a comparison of a terminal voltage of the battery to a clamp voltage. When the terminal voltage meets or exceeds the clamp voltage, a high time current of the charge current pulse can be decreased and the clamp voltage can be increased before providing a subsequent charge current pulse.

Abstract: A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.

Abstract: This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay.

Abstract: A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal.

Abstract: This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay.