Abstract: Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability that each interconnect model will be used to connect the pins of the net is evaluated. Tiles in the integrated circuit design are then assigned probabilities indicating the likelihood that each of the interconnect models will traverse the tiles. A map is then generated to indicate probabilistic routing characteristics (e.g., probabilities of wire congestion, interconnect component congestion, power densities, interconnect model usage) based on the probabilities assigned to each of the tiles in the integrated circuit design. The map may then be output (e.g., printed or otherwise displayed) to a user or stored for later use.

Abstract: Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of the edges based on required arrival time and design slack (S,T) pairs associated with the different timing paths. The required arrival time is a maximum time when associated with forward paths, and a minimum time when associated with backward paths. (S,T) pairs associated with some timing paths are discarded (i.e., the corresponding timing paths are trimmed) to reduce the complexity of the delay budget allocation computations. Remaining (S,T) pairs are used to determine scaling factors for significant timing paths through the edges. The smallest of the scaling factors for each edge can be multiplied by an initial delay associated with the edge to produce a delay budget allocation associated with the edge.

Abstract: Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability that each interconnect model will be used to connect the pins of the net is evaluated. Tiles in the integrated circuit design are then assigned probabilities indicating the likelihood that each of the interconnect models will traverse the tiles. A map is then generated to indicate probabilistic routing characteristics (e.g., probabilities of wire congestion, interconnect component congestion, power densities, interconnect model usage) based on the probabilities assigned to each of the tiles in the integrated circuit design. The map may then be output (e.g., printed or otherwise displayed) to a user or stored for later use.

Abstract: Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of the edges based on required arrival time and design slack (S,T) pairs associated with the different timing paths. The required arrival time is a maximum time when associated with forward paths, and a minimum time when associated with backward paths. (S,T) pairs associated with some timing paths are discarded (i.e., the corresponding timing paths are trimmed) to reduce the complexity of the delay budget allocation computations. Remaining (S,T) pairs are used to determine scaling factors for significant timing paths through the edges. The smallest of the scaling factors for each edge can be multiplied by an initial delay associated with the edge to produce a delay budget allocation associated with the edge.

Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.