Patents by Inventor Alvar A. Dean
Alvar A. Dean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8457156Abstract: A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.Type: GrantFiled: August 10, 2010Date of Patent: June 4, 2013Assignee: Cisco Technology, Inc.Inventors: John T. Chapman, Alvar A. Dean, Richard J. Santarpio, John P. Prokopik, Michael J. Healy
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Publication number: 20110051753Abstract: A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.Type: ApplicationFiled: August 10, 2010Publication date: March 3, 2011Applicant: Cisco Technology, Inc.Inventors: John T. Chapman, Alvar A. Dean, Richard J. Santarpio, John P. Prokopik, Michael J. Healy
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Publication number: 20100316104Abstract: A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.Type: ApplicationFiled: August 9, 2010Publication date: December 16, 2010Applicant: Cisco Technology, Inc.Inventors: John T. Chapman, Alvar A. Dean, Richard J. Santarpio, John P. Prokopik
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Patent number: 7782898Abstract: A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.Type: GrantFiled: February 4, 2003Date of Patent: August 24, 2010Assignee: Cisco Technology, Inc.Inventors: John T. Chapman, Alvar A. Dean, Richard J. Santarpio, John P. Prokopik, Michael J. Healy
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Patent number: 7478280Abstract: A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.Type: GrantFiled: December 13, 2007Date of Patent: January 13, 2009Assignee: International Business Machines CorporationInventors: Alvar A. Dean, Sebastian T. Ventrone
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Patent number: 7469395Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.Type: GrantFiled: December 7, 2007Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20080091994Abstract: A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.Type: ApplicationFiled: December 13, 2007Publication date: April 17, 2008Applicant: International Business Machines CorporationInventors: Alvar Dean, Sebastian Ventrone
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Publication number: 20080074147Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.Type: ApplicationFiled: December 7, 2007Publication date: March 27, 2008Inventors: John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Thomas Lepsic, Jagannathan Narasimhan, Scott Tetreault, Sebastian Ventrone
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Patent number: 7350108Abstract: A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing chips are disconnected from further testing and passing or failing chips are recorded.Type: GrantFiled: September 10, 1999Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Alvar A. Dean, Sebastian T. Ventrone
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Patent number: 7346875Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: GrantFiled: July 7, 2005Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20060038602Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.Type: ApplicationFiled: October 21, 2005Publication date: February 23, 2006Inventors: Anthony Bonaccio, John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Sebastian Ventrone
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Patent number: 6985004Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: GrantFiled: February 12, 2001Date of Patent: January 10, 2006Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20050262463Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: ApplicationFiled: July 7, 2005Publication date: November 24, 2005Inventors: John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Thomas Lepsic, Jagannathan Narasimhan, Scott Tetreault, Sebastian Ventrone
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Patent number: 6802033Abstract: A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.Type: GrantFiled: April 6, 1999Date of Patent: October 5, 2004Assignee: International Business Machines CorporationInventors: Claude L. Bertin, Alvar A. Dean, Kenneth J. Goodnow, Scott W. Gould, Patrick E. Perry, Wilbur D. Pricer, William R. Tonti
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Patent number: 6792582Abstract: Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria.Type: GrantFiled: November 15, 2000Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: John M Cohn, Alvar A. Dean, David J. Hathaway, David E. Lackey, Thomas M. Lepsic, Susan K. Lichtensteiger, Scott A. Tetreault, Sebastian T. Ventrone
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Publication number: 20040163129Abstract: A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.Type: ApplicationFiled: February 4, 2003Publication date: August 19, 2004Applicant: Cisco Technology, Inc.Inventors: John T. Chapman, Alvar A. Dean, Richard J. Santarpio, John P. Prokopik
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Patent number: 6711719Abstract: In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.Type: GrantFiled: August 13, 2001Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: John Maxwell Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas Michael Lepsic, Patrick Edward Perry, Scott A. Tetreault, Sebastian T. Ventrone
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Patent number: 6687883Abstract: A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.Type: GrantFiled: December 28, 2000Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: John M. Cohn, Alvar A. Dean, David J. Hathaway, Sebastian T. Ventrone
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Patent number: 6636995Abstract: A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit.Type: GrantFiled: July 13, 2000Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Alvar A. Dean, Joseph A. Iadanza, David E. Lackey, Sebastian T. Ventrone
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Publication number: 20030158714Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.Type: ApplicationFiled: February 12, 2001Publication date: August 21, 2003Inventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone