Patents by Inventor Alvin A. Joseph
Alvin A. Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862511Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.Type: GrantFiled: November 16, 2021Date of Patent: January 2, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Steven M. Shank, Siva P. Adusumilli, Alvin Joseph
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Patent number: 11842940Abstract: A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.Type: GrantFiled: January 25, 2021Date of Patent: December 12, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Ramsey Hazbun, Siva P. Adusumilli, Mark David Levy, Alvin Joseph
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Publication number: 20230223254Abstract: Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.Type: ApplicationFiled: January 10, 2022Publication date: July 13, 2023Inventors: Ramsey Hazbun, Mark Levy, Alvin Joseph, Siva P. Adusumilli
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Publication number: 20230154786Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.Type: ApplicationFiled: November 16, 2021Publication date: May 18, 2023Inventors: Steven M. Shank, Siva P. Adusumilli, Alvin Joseph
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Patent number: 11569170Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.Type: GrantFiled: October 7, 2020Date of Patent: January 31, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Siva P. Adusumilli, Mark David Levy, Ramsey Hazbun, Alvin Joseph, Steven Bentley
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Publication number: 20220238409Abstract: A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.Type: ApplicationFiled: January 25, 2021Publication date: July 28, 2022Inventors: RAMSEY HAZBUN, SIVA P. ADUSUMILLI, MARK DAVID LEVY, ALVIN JOSEPH
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Publication number: 20220108951Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.Type: ApplicationFiled: October 7, 2020Publication date: April 7, 2022Inventors: SIVA P. ADUSUMILLI, MARK DAVID LEVY, RAMSEY HAZBUN, ALVIN JOSEPH, STEVEN BENTLEY
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Publication number: 20210315588Abstract: The present invention relates to a first responder bracelet that includes a sleeve and a tassel both connected at one end and another end engages when user wears it. The bracelet unfolds into a tourniquet. The tourniquet includes a strap within a sleeve. The strap is fixed with a strap lock with a buckle at one end. Additionally, a twist lock is fixed to the strap at the other end. The twist lock is capable of twisting and engaging with the strap lock near the buckle area.Type: ApplicationFiled: April 13, 2021Publication date: October 14, 2021Inventor: Alvin Joseph Jolivette, JR.
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Patent number: 10062711Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.Type: GrantFiled: December 21, 2016Date of Patent: August 28, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Steven Shank, Alvin Joseph, Michel Abou-Khalil, Michael Zierak
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Publication number: 20180204926Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.Type: ApplicationFiled: March 15, 2018Publication date: July 19, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
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Publication number: 20180175064Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Steven Shank, Alvin Joseph, Michel Abou-Khalil, Michael Zierak
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Patent number: 9978849Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.Type: GrantFiled: December 29, 2015Date of Patent: May 22, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
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Patent number: 9968226Abstract: A bathroom fixture assembly comprising a plurality of rigid vertical members each comprising a first end configured to couple to a ceiling and a second end configured to extend downward beyond an upper edge of an outer wall of a basin of a bathtub or shower. The assembly may comprise a shower curtain channel configured to house a fully-functioning shower curtain. The assembly may further comprise one or more gates that may be used as grab bars and that may lock into position about a 180 degree range of motion around any of the rigid vertical members. The assembly may further comprise a seat, which may pivot from an upward position to a horizontal position when use is desired. The assembly may optionally comprise an exterior seat, cabinet, light, multi-use davit/hook, and/or physical therapy sky hook.Type: GrantFiled: January 6, 2017Date of Patent: May 15, 2018Inventor: Alvin Joseph Anderson
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Publication number: 20170221882Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.Type: ApplicationFiled: February 2, 2016Publication date: August 3, 2017Inventors: Ananth Sundaram, Balaji Swaminathan, Srikumar Konduru, Alvin Joseph, Michael Zierak
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Patent number: 9721948Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.Type: GrantFiled: February 2, 2016Date of Patent: August 1, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Ananth Sundaram, Balaji Swaminathan, Srikumar Konduru, Alvin Joseph, Michael Zierak
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Publication number: 20170186845Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.Type: ApplicationFiled: December 29, 2015Publication date: June 29, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Michel J. Abou-Khalil, Alan Bernard Botula, Blaine Jeffrey Gross, Mark David Jaffe, Alvin Joseph, Richard A. Phelps, Steven M. Shank, James Albert Slinkman
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Patent number: 8234606Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: GrantFiled: April 6, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson
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Publication number: 20110185330Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson
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Patent number: 7968975Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: GrantFiled: August 8, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson
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Publication number: 20100032809Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Applicant: International Business Machines CorporationInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson