Abstract: An error correction code for an array of N words of M bits each may be generated by: (i) for each word of the N words, computing a respective set of checkbits for single-error correction of such word; (ii) computing a set of bit-position-related checkbits comprising a bitwise logical exclusive OR of all of the sets of checkbits for single-error correction of the N words; (iii) for each word of the N words, computing a respective parity for the respective set of checkbits and the word itself in order to form a vector of N parity bits; (iv) computing a set of word-related checkbits for single-error correction of the vector of N parity bits; and (v) computing a cumulative parity bit comprising a parity calculation of the set of bit-position-related checkbits, the set of word-related checkbits, and the vector of N parity bits.

Abstract: An error correction code for an array of N words of M bits each may be generated by: (i) for each word of the N words, computing a respective set of checkbits for single-error correction of such word; (ii) computing a set of bit-position-related checkbits comprising a bitwise logical exclusive OR of all of the sets of checkbits for single-error correction of the N words; (iii) for each word of the N words, computing a respective parity for the respective set of checkbits and the word itself in order to form a vector of N parity bits; (iv) computing a set of word-related checkbits for single-error correction of the vector of N parity bits; and (v) computing a cumulative parity bit comprising a parity calculation of the set of bit-position-related checkbits, the set of word-related checkbits, and the vector of N parity bits.

Abstract: A portable audio device may be configured to measure load characteristics of headphones. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load. These characteristics may be measured by an audio component, such as an audio codec chip or integrated circuit (IC) controller, and reported to software or firmware executing on a processor coupled to the audio component. The software or firmware may then take action based on the measured load characteristics. For example, the load characteristics may be compared to a database of headphones and their known load characteristics to determine a particular headphone model or type of headphone attached to the audio output. The processor may then apply an appropriate equalization curve.

Abstract: An electronic device may be configured to identify a load coupled to the device. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load to identify the load. The device may then take action based on the identification of the load. For example, a specific transducer may be identified as coupled to the electronic device and an appropriate equalization curve applied to an audio output of the device. The measurement of characteristics of the load may include controlling a reference generator according to a search algorithm, such as a step ramp or binary search, to identify the load. An analog-to-digital converter (ADC) may operate through the search algorithm to provide feedback to digital circuitry regarding how to proceed through the search algorithm to identify the load.

Abstract: An electronic device may be configured to identify a load coupled to the device. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load to identify the load. The device may then take action based on the identification of the load. For example, a specific transducer may be identified as coupled to the electronic device and an appropriate equalization curve applied to an audio output of the device. The measurement of characteristics of the load may include controlling a reference generator according to a search algorithm, such as a step ramp or binary search, to identify the load. An analog-to-digital converter (ADC) may operate through the search algorithm to provide feedback to digital circuitry regarding how to proceed through the search algorithm to identify the load.

Abstract: A portable audio device may be configured to measure load characteristics of headphones. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load. These characteristics may be measured by an audio component, such as an audio codec chip or integrated circuit (IC) controller, and reported to software or firmware executing on a processor coupled to the audio component. The software or firmware may then take action based on the measured load characteristics. For example, the load characteristics may be compared to a database of headphones and their known load characteristics to determine a particular headphone model or type of headphone attached to the audio output. The processor may then apply an appropriate equalization curve.

Abstract: An electronic device may be configured to identify a load coupled to the device. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load to identify the load. The device may then take action based on the identification of the load. For example, a specific transducer may be identified as coupled to the electronic device and an appropriate equalization curve applied to an audio output of the device. The measurement of characteristics of the load may include controlling a reference generator according to a search algorithm, such as a step ramp or binary search, to identify the load. An analog-to-digital converter (ADC) may operate through the search algorithm to provide feedback to digital circuitry regarding how to proceed through the search algorithm to identify the load.

Abstract: An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A digital controller for controlling the operation of a DC-DC switching converter is disclosed. A digital feedback control system is provided for receiving an analog input voltage representing the output of the switching converter and digitally processing the analog input voltage by comparing it to a reference voltage and then determining analog drive signals to control the operation of the switching converter to provide a regulated output. The digital feedback control system operates in accordance with predetermined operating parametrics. The digital feedback control system also has monitoring inputs and control inputs. A microcontroller monitors the operation of the digital feedback control system and is able to change the operating parametrics under certain predetermined conditions.

Abstract: A monolithic digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A system for monitoring interrupts to a processor includes a multiplexer having a plurality of inputs connected to receive various analog inputs. The multiplexer further has an output which is programmably connected to one of the plurality of inputs responsive to a control signal. An analog to digital converter is connected to the output of the multiplexer for converting an analog signal at the output to a digital signal. An auto-scan block generates the control signal provided to the multiplexer. The control signal selects ones of the plurality of inputs of the multiplexer for connection to the output in a programmably defined order.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the pins for comparing the analog voltage level thereon with a reference voltage.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource.

Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.