Patents by Inventor Alvin I. Chen

Alvin I. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7835890
    Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: November 16, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lifeng Wu, Zhihong Liu, Alvin I. Chen, Jeong Y. Choi, Bruce W. McGaughy
  • Publication number: 20090299716
    Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 3, 2009
    Inventors: Zhihong Liu, Lifeng Wu, Jeong Y. Choi, Ping Chen, Alvin I. Chen, Gang Zhang
  • Patent number: 7567891
    Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 28, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhihong Liu, Lifeng Wu, Jeong Y. Choi, Ping Chen, Alvin I. Chen, Gang Zhang
  • Patent number: 7292968
    Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: November 6, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lifeng Wu, Zhihong Liu, Alvin I. Chen, Jeong Y. Choi, Bruce W. McGaughy
  • Patent number: 7219045
    Abstract: The present invention is directed to methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects by allowing design rules on degradation to be included in the netlist. Once the hot-carrier circuit simulation is launched, the rules are checked and the reliability design rule violations are reported. The process can be performed on either the layout or schematic window. The design rule criteria can be any device parameter and can be expressed in absolute or relative terms. The criteria can be based on device type, model card name, instance geometry, or temperature. Additionally, values can be set prior to beginning the simulation.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: May 15, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lifeng Wu, Jeong Y. Choi, Alvin I. Chen, Jingkun Fang
  • Publication number: 20030055621
    Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.
    Type: Application
    Filed: April 11, 2001
    Publication date: March 20, 2003
    Inventors: Lifeng Wu, Zhihong Liu, Alvin I. Chen, Jeong Y. Choi, Bruce W. McGaughy