Patents by Inventor Alvin Leng Sun Loke
Alvin Leng Sun Loke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160285453Abstract: In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor. The driver also comprises a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.Type: ApplicationFiled: December 2, 2015Publication date: September 29, 2016Inventors: Stephen Clifford Thilenius, Patrick Isakanian, Alvin Leng Sun Loke, Thomas Clark Bryan, LuVerne Ray Peterson
-
Publication number: 20160269017Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.Type: ApplicationFiled: July 29, 2015Publication date: September 15, 2016Inventors: Alvin Leng Sun Loke, Bo Yu, Stephen Clifford Thilenius, Reza Jalilizeinali, Patrick Isakanian
-
Patent number: 9350339Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.Type: GrantFiled: July 18, 2014Date of Patent: May 24, 2016Assignee: QUALCOMM IncorporatedInventors: Thomas Clark Bryan, Alvin Leng Sun Loke, Stephen Knol, Gregory Francis Lynch, Tin Tin Wee, LuVerne Ray Peterson, Yue Li
-
Patent number: 9274534Abstract: A voltage regulator includes a pass element having a control input coupled to a control node and operable to generate an output voltage at an output node, a negative feedback amplifier operable to receive a reference voltage and the output voltage and generate a signal at the control node based on a difference between the reference voltage and the output voltage, and a noise cancellation circuit coupled to the control node and the output node and operable to generate a bias current at the control node based on the output voltage.Type: GrantFiled: December 21, 2012Date of Patent: March 1, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Emerson S. Fang, Alvin Leng Sun Loke
-
Publication number: 20160025807Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.Type: ApplicationFiled: July 23, 2014Publication date: January 28, 2016Inventors: Alvin Leng Sun Loke, Thomas Clark Bryan, Reza Jalilizeinali, Tin Tin Wee, Stephen Robert Knol, LuVerne Ray Peterson
-
Patent number: 9244875Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.Type: GrantFiled: July 18, 2014Date of Patent: January 26, 2016Assignee: QUALCOMM IncorporatedInventors: Alvin Leng Sun Loke, Tin Tin Wee, Thomas Clark Bryan
-
Patent number: 9245870Abstract: A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.Type: GrantFiled: October 17, 2014Date of Patent: January 26, 2016Assignee: QUALCOMM IncorporatedInventors: LuVerne Ray Peterson, Thomas Clark Bryan, Alvin Leng Sun Loke, Tin Tin Wee, Gregory Francis Lynch, Stephen Robert Knol
-
Publication number: 20160019179Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.Type: ApplicationFiled: July 18, 2014Publication date: January 21, 2016Inventors: Alvin Leng Sun Loke, Tin Tin Wee, Thomas Clark Bryan
-
Publication number: 20160020759Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.Type: ApplicationFiled: July 18, 2014Publication date: January 21, 2016Inventors: Thomas Clark Bryan, Alvin Leng Sun Loke, Stephen Knol, Gregory Francis Lynch, Tin Tin Wee, LuVerne Ray Peterson, Yue Li
-
Publication number: 20150237709Abstract: Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: QUALCOMM INCORPORATEDInventors: Arpit Mittal, Alvin Leng Sun Loke, Mehdi Saeidi, Patrick Drennan
-
Publication number: 20140176098Abstract: A voltage regulator includes a pass element having a control input coupled to a control node and operable to generate an output voltage at an output node, a negative feedback amplifier operable to receive a reference voltage and the output voltage and generate a signal at the control node based on a difference between the reference voltage and the output voltage, and a noise cancellation circuit coupled to the control node and the output node and operable to generate a bias current at the control node based on the output voltage.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Emerson S. Fang, Alvin Leng Sun Loke
-
Publication number: 20140159200Abstract: An embodiment of a high-density, stacked, planar metal-insulator-metal (MIM) capacitor structure includes a stack of planar electrodes and interposing dielectric layers. Vertically-alternating electrodes are horizontally-staggered, and vias are formed through the multiple electrodes, so that electrical connection is made circumferentially through the via sidewalls to multiple electrodes through which a given via passes. An MIM capacitor incorporating a multiple-level capacitor stack may be fabricated by repeated usage of the same mask operation for each incremental capacitor stack level, and without requiring additional masks beyond those utilized for the first such level.Type: ApplicationFiled: December 28, 2012Publication date: June 12, 2014Inventors: Alvin Leng Sun Loke, Tin Tin Wee
-
Publication number: 20140049292Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicants: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Petre Popescu, Emerson S. Fang, Bruce A. Doyle, Alvin Leng Sun Loke, Shawn Searles
-
Patent number: 8466536Abstract: A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement.Type: GrantFiled: October 14, 2010Date of Patent: June 18, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Alvin Leng Sun Loke, Tin Tin Wee
-
Publication number: 20120091558Abstract: A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement.Type: ApplicationFiled: October 14, 2010Publication date: April 19, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Alvin Leng Sun LOKE, Tin Tin WEE
-
Patent number: 8134417Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.Type: GrantFiled: June 10, 2010Date of Patent: March 13, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Meei-Ling Chiang, Dennis M. Fischette, Alvin Leng Sun Loke, Michael M. Oshima
-
Publication number: 20110304407Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.Type: ApplicationFiled: June 10, 2010Publication date: December 15, 2011Inventors: Meei-Ling Chiang, Dennis M. Fischette, Alvin Leng Sun Loke, Michael M. Oshima
-
Publication number: 20110133719Abstract: According to one embodiment, a voltage reference circuit operable with a low voltage supply comprises an op-amp powered by the low voltage supply and a feedback branch including a transistor driven by an output of the op-amp. The feedback branch couples the low voltage supply to ground through the transistor and at least a rectifying device situated between a reference node of the feedback branch and ground. An input of the op-amp is coupled to the reference node by a voltage divider. In one embodiment, the voltage reference circuit further comprises a reference branch coupling a second reference node to ground through at least a second rectifying device, and wherein a second input of the op-amp is coupled to the second reference node by a second voltage divider.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Inventors: Alvin Leng Sun Loke, Tin Tin Wee, Chad Owen Lackey, Bruce Andrew Doyle
-
Patent number: 7782166Abstract: Cross-coupled first and second helical inductors formed in an IC. The cross-coupled first and second helical inductors comprise a first helical conductor having a first portion and a second portion, and a second helical conductor having a first portion and a second portion. The second helical conductor is in close proximity to the first helical conductor. The first helical inductor is formed by the first portion of the first helical conductor and the second portion of the second helical conductor. The second helical inductor is formed by the second portion of the first helical conductor and the first portion of the second helical conductor.Type: GrantFiled: December 31, 2008Date of Patent: August 24, 2010Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Alvin Leng Sun Loke, Philip Wilfred Fisher, Robert James Martin
-
Publication number: 20090108978Abstract: Cross-coupled first and second helical inductors formed in an IC. The cross-coupled first and second helical inductors comprise a first helical conductor having a first portion and a second portion, and a second helical conductor having a first portion and a second portion. The second helical conductor is in close proximity to the first helical conductor. The first helical inductor is formed by the first portion of the first helical conductor and the second portion of the second helical conductor. The second helical inductor is formed by the second portion of the first helical conductor and the first portion of the second helical conductor.Type: ApplicationFiled: December 31, 2008Publication date: April 30, 2009Applicant: Avago Technologies General IP (Singapore) Pte. Ltd. (Company Registration No. 200512430D)Inventors: Alvin Leng Sun Loke, Philip Wilfred Fisher, Robert James Martin