Abstract: A method for adjusting the leakage current of insulated gate field effect transistors comprised of silicon mesas epitaxially formed on a sapphire substrate, wherein the leakage current of a P channel transistor is increased by preoxidizing the silicon prior to standard processing and/or wherein the leakage current is decreased by annealing the silicon in a reducing atmosphere in addition to standard processing steps. The leakage current of an N channel transistor is reduced by preoxidizing the silicon of the transistor prior to forming the transistor and/or is increased by annealing in a reducing atmosphere in addition to the steps necessary for forming the transistor.

Abstract: Capacitance is measured using a conventional meter while a DC bias voltage in a range from 0 to 10K volts is applied across the capacitance under test. An LC series resonant circuit is disposed between the capacitance under test and one input of the capacitance meter to provide a low impedance path for the 1 MHz test signal produced by the capacitance meter. P-I-N diodes are disposed across the input terminals of the capacitance meter to shunt the discharged energy from the resonant circuit capacitance should the capacitor under test short circuit. A resistance is in series with the resonant circuit to provide a voltage divider to lower the voltage appearing across the capacitance-meter input terminals to a value below the damage-threshold voltage level of the capacitance-meter.