Patents by Inventor Alvin P. Short

Alvin P. Short has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Increase in deep trench capacitance by a central ground electrode
    Patent number: 6930345
    Abstract: A semiconductor device includes a trench formed in a substrate, and a diffusion region surrounding the trench to form a buried plate. A first conductive material is formed in the trench and connects to the buried plate through a bottom of the trench to form a first electrode. A second conductive material is disposed in the trench to form a second electrode. A node dielectric layer is formed between the first electrode and the second electrode.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: August 16, 2005
    Assignee: Infineon Technologies Richmond, LP
    Inventor: Alvin P. Short
  • Increase in deep trench capacitance by a central ground electrode
    Publication number: 20020167045
    Abstract: A semiconductor device includes a trench formed in a substrate, and a diffusion region surrounding the trench to form a buried plate. A first conductive material is formed in the trench and connects to the buried plate through a bottom of the trench to form a first electrode. A second conductive material is disposed in the trench to form a second electrode. A node dielectric layer is formed between the first electrode and the second electrode.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 14, 2002
    Inventor: Alvin P. Short
  • Three-dimensional device layout with sub-groundrule features
    Patent number: 5893735
    Abstract: Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: April 13, 1999
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Reinhard J. Stengl, Erwin Hammerl, Jack A. Mandelman, Herbert L. Ho, Radhika Srinivasan, Alvin P. Short, Bernhard Poschenrieder
  • Buried strap formation in a DRAM trench capacitor
    Patent number: 5844266
    Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: December 1, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Reinhard Stengl, Erwin Hammerl, Herbert L. Ho, Jack A. Mandelman, Radhika Srinivasan, Alvin P. Short
  • Buried-strap formation in a dram trench capacitor
    Patent number: 5827765
    Abstract: A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: October 27, 1998
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Reinhard Stengl, Erwin Hammerl, Herbert L. Ho, Jack A. Mandelman, Radhika Srinivasan, Alvin P. Short
  • Three-dimensional device layout having a trench capacitor
    Patent number: 5792685
    Abstract: Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: August 11, 1998
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Erwin Hammerl, Jack A. Mandelman, Bernhard Poschenrieder, Alvin P. Short, Radhika Srinivasan, Reinhard J. Stengl, Herbert L. Ho