Abstract: Comb filter arrangements are provided for separating frequency interleaved signal components of a video signal. A video signal is sampled at a rate which satisfies the Nyquist criterion for the bandwidth of the signal, and the resultant signal samples are applied to a bandpass filter. The bandpass filter produces a filtered signal restricted to a portion of the original video band. The filtered signal is subsampled at a rate which satisfies the Nyquist criterion for the information of the restricted passband, producing replicas of the restricted passband beginning approximately at zero Hertz and extending upward in frequency about frequencies which are multiples of the subsampling frequency and its harmonics. The subsampled information in the replicated passbands is comb filtered, and the comb filtered signals are interpolated up to the original sampling rate of the video signal.

Abstract: A synchronizing pulse processor accepts integrated and differentiated composite sync signal inputs of either positive or negative polarity. Processed horizontal and vertical sync pulses are produced which have a single predetermined polarity independent of the polarity of the composite sync signal. The polarity of the differentiated composite sync signal is used to select the reference level for the vertical sync pulse threshold detector. The sync processor may be formed as a part of an integrated circuit and require only two input interface terminals regardless of composite sync signal polarity.

Abstract: An automatic gain control arrangement is provided for an analog to digital (A/D) converter in a television signal processing system. A gain-controlled source of analog signals applies a video information signal to the input of an A/D converter. The A/D converter produces digitized video signal samples at an output which is coupled to a digital peak detector. The digital peak detector detects the level of the digital samples of the synchronizing signal components. The detected sync signal level is compared with a desired value or range of values. If the detected sync signal level is not at the desired level or is outside the desired range, the count of a counter is incremented or decremented accordingly. The count of the counter is converted to an analog voltage which is applied to the gain-controlled signal source to control the level of the analog signal applied to the A/D converter.

Abstract: A switching voltage regulator control circuit incorporating a switching device including a control electrode comprises means for sampling the output voltage of the regulator. A horizontal rate signal is combined with the sampled output voltage to provide a horizontal rate sample signal. The sample signal is compared to a predetermined reference and provides a control signal for the switching device which is applied to one input of a gating means. A second horizontal rate signal is applied to a second input of the gating means and disables it during a portion of each horizontal deflection interval.

Abstract: A horizontal deflection turn-on circuit operates in the absence of trigger pulse normally derived by an AFPC loop. Under normal operation, the AFPC loop generates the trigger pulses based on a synchronized phase relationship with sampled flyback pulses. During receiver start-up, the flyback pulses are not present and no trigger pulses are generated. The turn on circuit provides auxiliary pulses which occur later in time than the normal occurrence of the trigger pulses. Means are provided for applying the auxiliary pulses to the horizontal deflection circuit only in the absence of normal trigger pulses.

Abstract: In a television receiver horizontal deflection circuit, the deflection circuit oscillator includes an LC resonant tank network that is excited into sustained oscillation to develop an oscillator alternating output signal. A high voltage generator is responsive to the oscillator output signal and develops a picture tube ultor voltage at an ultor terminal. An ultor voltage representative signal is applied to the input of a disabling latch circuit of a television receiver high voltage protection circuit. First and second diodes are coupled across the inductive portion of the oscillator tank network, with the cathodes of the two diodes being coupled together at a junction in common with the output terminal of the disabling latch. If the ultor voltage exceeds a predetermined level, the latch is energized, forward biasing both diodes to provide a short-circuit across the tank network.

Abstract: A start-up circuit for a power supply used in a television receiver controls the operation of the power supply during a start-up interval. The power supply is disabled by the start-up circuit at a first voltage level until a capacitor is charged to a predetermined second voltage level. The power supply is then enabled, disabling the start-up circuit, and discharging the capacitor. The power supply continues to operate until the capacitor is discharged below an intermediate voltage level at which point the power supply is disabled and the start-up circuit again becomes operative to allow the capacitor to recharge.

Abstract: A digital-to-analog converter for use in a television tuning system to convert bits stored in a register to a corresponding tuning voltage includes a counter for generating binary pulse signals having pulses with durations proportional to powers of 2 and a plurality of selection gates for selecting ones of the binary pulse signals in accordance with the states of respective bits stored in the register to generate a plurality of output pulse signals each having G pulses with durations proportional to ##EQU1## where n is the number of the respective bit. The output pulse signals are justified with respect to each other by position-determining gates and combined to form G clusters of contiguous but non-overlapping pulses. The resulting pulse signal is filtered by a low/pass filter to derive the tuning voltage. G is selected as a compromise value consistent with both reasonable temperature stability and a reasonably fast filter response.

Abstract: A television horizontal deflection synchronizing system uses two phase-lock loops. A horizontal oscillator operating at a frequency greater than the horizontal frequency is counted and a bilevel signal near the horizontal frequency is generated. A first phase-lock loop having a relatively long time constant controls the oscillator to maintain the bilevel signal in frequency and phase synchronism with horizontal synchronizing signals. In order to compensate for load-dependent variations in the delay of the horizontal deflection stage, a second phase-lock loop is used. The second phase-lock loop includes a phase detector, one input of which is coupled to an output of the first phase-lock loop and a second input of which is coupled to the deflection circuit for responding to the retrace pulse for enabling the phase detector to produce a current of a first polarity when the bilevel signal has a first value and a current of a second polarity when the bilevel signal has a second value.

Abstract: A circuit arrangement is provided for multiplexing an input signal and an output signal through a single circuit terminal. Means are coupled to the terminal for selectively applying first input signals to the terminal of a signal level included within a first range of signal levels. Means including a first transistor having an input electrode coupled to a second signal source and an output electrode coupled to the terminal are provided for developing, in the absence of the first input signals, output signals at the terminal which occupy a second range of signal levels which is exclusive of the first range. A second transistor has an input electrode coupled to the terminal and an output electrode, and is biased to be responsive to signals at the terminal which occupy the first range of signal levels.

Abstract: A television horizontal deflection system and a switched-mode power supply are provided which share a single sawtooth waveform generator for the generation of delayed deflection signals and delayed power supply gating signals, respectively. The sawtooth waveform generator has an input coupled to receive pulses which are maintained in phase and frequency synchronism with the sync pulses of the video signal. The sawtooth waveform is applied to a comparator in the horizontal deflection system where it is compared with a D.C. voltage resulting from the phase comparison of the sync and flyback pulses to determine the time of delayed generation of the succeeding horizontal deflection signals. The sawtooth waveform is also applied to a comparator in the power supply to determine the time of delayed generation of the succeeding gating signals for the SCR or like device. By selecting a time constant for the phase adjustment between sync and flyback in the deflection system which is smaller (i.e.

Abstract: A pulse generator is provided which may be advantageously used to produce a deflection drive signal in a television receiver. A capacitor is initially charged to a reference voltage level. Prior to the time at which the output pulse is to be generated, the capacitor is charged from a current source for a known time duration at a first rate. At the end of the charging interval, the capacitor has accumulated a known increment of charge proportional to the charge interval, and a new voltage level is established across the capacitor. The generator is now prepared to produce an output pulse. At a subsequent time, when the output pulse is needed, the capacitor is discharged at a second rate by a second current source. During the time interval that the second current source is discharging the capacitor, an output pulse is produced by the generator.

Abstract: A differential amplifier is provided, including first and second emitter coupled transistors responsive to an input signal applied to one of their base electrodes, and a current source transistor having its collector-to-emitter path serially coupled between the coupled emitters of the first and second transistors and a point of reference potential. A current repeater circuit is coupled between the collector electrodes of the first and second transistors which comprises a current mirror for replicating the collector current of the first transistor. The current mirror includes third and fourth transistors having respective collector electrodes coupled to the collector electrodes of the first and second transistors, respectively, the base electrode of the third transistor being coupled to the base electrode of the fourth transistor, and a resistor for coupling the emitter electrode of at least one of the third and fourth transistors to a source of supply voltage.

Abstract: An AFPC loop for TV horizontal oscillator suitable for use with sync signals subject to timing instability includes means for maintaining a long response time during the equalizing and vertical sync intervals to reduce drift, and shortens the loop response time after the second equalizing pulse interval for maximum correction.

Abstract: A gating circuit coupled to the phase detector of an AFPC loop prevents response of the phase detector to alternate sync pulses during the equalizing and vertical sync pulse interval.

Abstract: A variable-frequency oscillator includes an oscillator portion coupled to a phase shifter and a controllable gain device for controlling the amount of phase-shifted signal reintroduced to the oscillator. The oscillator includes first and second transistors coupled at their emitters to a current source. The emitters of third and fourth transistors are coupled to bases of the first and second transistors, respectively. The base of the third transistor is coupled to a voltage source, and the base of the fourth transistor couples to the collector of the first to form a regenerative loop capable of oscillation. A parallel-resonant circuit is coupled between the collector of the first transistor and the voltage source for establishing a frequency-sensitive phase characteristic in the loop by which the quiescent frequency is determined. The phase shifter is coupled to a point on the regenerative loop.

Abstract: A television horizontal AFPC loop includes a filter, the time constant of which can be switched at the vertical rate for improved operation from standard broadcast signals and from video tape recorders. A transistor switch introduces a voltage offset which perturbs the AFPC filtered oscillator control voltage. The perturbation is reduced by introducing a second offset voltage for reducing the perturbation and improving the synchronization of the oscillator with the synchronizing signals.

Abstract: A channel number display arrangement for a television receiver includes a multiplexer for alternately coupling binary signals representing the tens and units digits of the channel number of a selected channel to a single decoder and driver arrangement. To reduce visible effects of switching transients, the switching operation of the multiplexer is synchronized with respect to the receiver's deflection signals so that switching transients occur during horizontal retrace intervals in which the receiver's electron beams are normally blanked. In addition, keyed AGC circuitry, normally activated during the horizontal retrace intervals, is inhibited during the switching operation so that it is not erroneously set up in response to switching transients.

Abstract: A differential sample-and-hold circuit includes first and second emitter-coupled transistors the bases of which are coupled to the signal source to be sampled. A gated circuit source coupled to the joined emitters supplies operating current in the sampling mode and supplies no current in the holding mode. First and second rectifiers each serially coupled with a resistor are coupled between a reference voltage and the collectors of the first and second transistors, respectively. A hold capacitor is coupled between the collectors of the transistors.

Abstract: A relatively high speed, high density integrated circuit for dividing the frequency of an alternating signal includes first and second semiconductor boats formed on a substrate. The first boat includes a plurality of transistors having the semiconductor material of the boat as a common emitter region. The second boat includes a plurality of transistors having the semiconductor material of the boat as a common collector region. Pairs of transistors of the first boat and pairs of transistors of the second boat are coupled together in cross coupled configurations to form flip-flop stages. Complementary clock signals derived from the alternating signal are coupled to alternate stages. In each stage, the pair of transistors of the second boat are arranged as emitter followers to bias the pair of transistors in the first boat so that only one transistor of the pair is conductive at a time independent of the associated clock signal level.