Abstract: A system for predicting and summarizing medical events from electronic health records includes a computer memory storing aggregated electronic health records from a multitude of patients of diverse age, health conditions, and demographics including medications, laboratory values, diagnoses, vital signs, and medical notes. The aggregated electronic health records are converted into a single standardized data structure format and ordered arrangement per patient, e.g., into a chronological order. A computer (or computer system) executes one or more deep learning models trained on the aggregated health records to predict one or more future clinical events and summarize pertinent past medical events related to the predicted events on an input electronic health record of a patient having the standardized data structure format and ordered into a chronological order.

Abstract: An interface for an integrated circuit (IC) device. The interface includes a scrambler to combine a plurality of plaintext data streams and a pseudorandom key sequence. The scrambler includes a pseudorandom number (PRN) source and a combiner. The PRN source provides a pseudorandom number. The pseudorandom key sequence is based on the pseudorandom number. The combiner receives the plurality of plaintext data streams in parallel and output a corresponding plurality of ciphertext data streams in parallel to another IC device interface. The interface also may include a descrambler to separate a pseudorandom key sequence out of a plurality of parallel ciphertext data streams. By scrambling plaintext data streams and descrambling ciphertext data streams in parallel, the data transmission rate on the IC device may be slower than a data transmission rate used to transfer data between IC devices.

Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.