Abstract: Disclosed is a fungicidal composition comprising (a) at least one compound selected from the compounds of Formula 1, including all geometric and stereoisomers, tautomers, A-oxides, and salts thereof, wherein E, L, J, A and T are as defined in the disclosure; and (b) at least one additional fungicidal compound. Also disclosed is a method for controlling plant diseases caused by fungal plant pathogens comprising applying to the plant or portion thereof, or to the plant seed, a fungicidally effective amount of a compound of Formula 1, an A-oxide, or salt thereof (e.g., as a component in the aforesaid composition). Also disclosed is a composition comprising: (a) at least one compound selected from the compounds of Formula 1 described above, A-oxides, and salts thereof; and at least one invertebrate pest control compound or agent.

Abstract: Techniques for visual software development are disclosed, including: (a) generating, by a visual code editor, (1) a data model of a plurality of code elements in a set of source code and (2) a kernel for execution of the set of source code; (b) based on a subset of the set of source code, the data model, and the kernel, generating an adjustable graphical user interface (GUI) form control; (c) presenting the adjustable GUI form control in alignment with the set of source code in a GUI of the visual code editor; and (d) responsive to user input in the GUI to adjust the adjustable GUI form control: (1) modifying the subset of source code and the data model according to the user input; (2) updating the presentation of the set of source code in the GUI to reflect the modified subset of source code; and (3) executing the modified set of source code, thereby updating variable values within the kernel.

Abstract: Techniques for visual software development are disclosed, including: generating, by a visual code editor, a data model of code elements in a set of source code; based on the data model, generating an adjustable graphical user interface (GUI) control corresponding to a subset of the set of source code; presenting the adjustable GUI control in a GUI of the visual code editor; and responsive to user input in the GUI to adjust the adjustable GUI control, modifying the set of source code according to the user input and executing the modified set of source code.

Abstract: Processes and compositions for the therapeutic treatment of pathogenic Gram-negative bacterial infection are provided whereby argininosuccinate synthetase or PEGylated argininosuccinate synthetase is administered to a subject to inactivate endotoxin thereby reducing the likelihood of bacterial sepsis and improving patient outcome.

Abstract: Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.

Abstract: Processes and compositions for the therapeutic treatment of pathogenic Gram-negative bacterial infection are provided whereby argininosuccinate synthetase or PEGylated argininosuccinate synthetase is administered to a subject to inactivate endotoxin thereby reducing the likelihood of bacterial sepsis and improving patient outcome.

Abstract: Processes and compositions for the therapeutic treatment of pathogenic Gram-negative bacterial infection are provided whereby arginino succinate synthetase or PEGylated arginino succinate synthetase is administered to a subject to inactivate endotoxin thereby reducing the likelihood of bacterial sepsis and improving patient outcome.

Abstract: A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal.

Abstract: A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal.

Abstract: Processes and compositions for the therapeutic treatment of pathogenic Gram-negative bacterial infection are provided whereby arginino succinate synthetase or PEGylated arginino succinate synthetase is administered to a subject to inactivate endotoxin thereby reducing the likelihood of bacterial sepsis and improving patient outcome.

Abstract: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

Abstract: A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Abstract: ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Abstract: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: A system and business method for enabling photolabs to provide digital image processing services, and at the same time, to provide the photolabs with the ability to use their own branding in connection with their services and to the control of all business aspects of the service, including the creation of a customized website, digital image product offerings, branding, pricing, promotions, advertisements, and film prints and related image imprinted product fulfillment.

Abstract: The invention generally provides data security network system and method integrated with a browser. A preferred embodiment of the method according to the invention primarily comprises the steps of calling a server having at least a first cabinet file and a second cabinet file from a client computer, directing the first cabinet file to the client computer by the server, displaying a data security control on an Internet browser at the client computer, activating the data security control, redirecting the client computer's browser to a specific web page, popping up the browser with embedded control components producing a scanning dialog box, and scanning the client computer.